From: Jonas Karlman Date: Tue, 30 Apr 2024 15:30:23 +0000 (+0000) Subject: rockchip: rk3399: Include uart related pinctrl nodes in TPL/SPL X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=fa903919d23fb2467730e864321180f7442d6d71;p=u-boot.git rockchip: rk3399: Include uart related pinctrl nodes in TPL/SPL The initial serial console UART iomux is typically configured in board_debug_uart_init() at TPL stage on Rockchip platform. Later stages typically use pinctrl driver to configure iomux UART once again based on the control FDT. Include uart related pinctrl nodes in TPL/SPL control FDT to make it possible for pinctrl driver to configure UART iomux at TPL/SPL stage. Following debug log message may also be seen at U-Boot pre-reloc stage: ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19 This can be resolved by including bootph prop for U-Bood pre-reloc phase (bootph-some-ram or bootph-all). However, this has intentionally been excluded due to including it unnecessarily slows down boot around 200-400 ms. Also add the clock-frequency prop similar to what has been done for other Rockchip SoCs. Signed-off-by: Jonas Karlman Reviewed-by: Kever Yang --- diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi index 390cf24152..d1912a2ef6 100644 --- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi +++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi @@ -113,4 +113,20 @@ &uart0 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart0_cts { + bootph-pre-sram; + bootph-pre-ram; +}; + +&uart0_rts { + bootph-pre-sram; + bootph-pre-ram; +}; + +&uart0_xfer { + bootph-pre-sram; + bootph-pre-ram; }; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 9815dc53e8..b39fe39fa2 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -136,6 +136,12 @@ &uart2 { bootph-all; + clock-frequency = <24000000>; +}; + +&uart2c_xfer { + bootph-pre-sram; + bootph-pre-ram; }; &vopb {