From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Sun, 12 Apr 2020 19:20:31 +0000 (+0200)
Subject: net: rtl8139: Rework eeprom_delay() macro
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=f80f4e4d729252eb6124e1afb5dde9f74c35c994;p=u-boot.git

net: rtl8139: Rework eeprom_delay() macro

The macro assumes ee_addr variable to be present when it's being
used. Rework the macro into a function instead and pass it an
argument specifying the register base address, to make it future
proof for DM conversion.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---

diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c
index 9898f20c39..ff014ade88 100644
--- a/drivers/net/rtl8139.c
+++ b/drivers/net/rtl8139.c
@@ -73,6 +73,7 @@
 
 #include <common.h>
 #include <cpu_func.h>
+#include <linux/types.h>
 #include <malloc.h>
 #include <net.h>
 #include <netdev.h>
@@ -297,18 +298,20 @@ static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
 #define EE_DATA_READ	0x01	/* EEPROM chip data out. */
 #define EE_ENB		(0x80 | EE_CS)
 
-/*
-	Delay between EEPROM clock transitions.
-	No extra delay is needed with 33MHz PCI, but 66MHz may change this.
-*/
-
-#define eeprom_delay()	inl(ee_addr)
-
 /* The EEPROM commands include the alway-set leading bit. */
 #define EE_WRITE_CMD	5
 #define EE_READ_CMD	6
 #define EE_ERASE_CMD	7
 
+static void rtl8139_eeprom_delay(uintptr_t regbase)
+{
+	/*
+	 * Delay between EEPROM clock transitions.
+	 * No extra delay is needed with 33MHz PCI, but 66MHz may change this.
+	 */
+	inl(regbase + RTL_REG_CFG9346);
+}
+
 static int read_eeprom(int location, int addr_len)
 {
 	int i;
@@ -318,30 +321,30 @@ static int read_eeprom(int location, int addr_len)
 
 	outb(EE_ENB & ~EE_CS, ee_addr);
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	/* Shift the read command bits out. */
 	for (i = 4 + addr_len; i >= 0; i--) {
 		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
 		outb(EE_ENB | dataval, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 		outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
 	outb(EE_ENB, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 
 	for (i = 16; i > 0; i--) {
 		outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 		retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
 		outb(EE_ENB, ee_addr);
-		eeprom_delay();
+		rtl8139_eeprom_delay(ioaddr);
 	}
 
 	/* Terminate the EEPROM access. */
 	outb(~EE_CS, ee_addr);
-	eeprom_delay();
+	rtl8139_eeprom_delay(ioaddr);
 	return retval;
 }