From: Andreas Dannenberg <dannenberg@ti.com>
Date: Wed, 14 Jun 2023 22:28:53 +0000 (-0500)
Subject: net: ti: am65-cpsw-nuss: Use dedicated port mode control registers
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=edacf6a44d2383f9137a99ffdf61a24de4a47307;p=u-boot.git

net: ti: am65-cpsw-nuss: Use dedicated port mode control registers

The different CPSW sub-system Ethernet ports have different PHY mode
control registers. In order to allow the modes to get configured
independently only the register for the port in question must be
accessed, otherwise we would just be re-configuring the mode for port 1,
while leaving all others at their power-on defaults. Fix this issue by
adding a port-number based offset to the mode control base register
address based on the fact that the control registers for the different
ports are spaced exactly 0x4 bytes apart.

Fixes: 9d0dca1199d1 ("net: ethernet: ti: Introduce am654 gigabit eth switch subsystem driver")
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index f674b0baa3..523a4c9f91 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -223,6 +223,8 @@ out:
 	return phy->link;
 }
 
+#define AM65_GMII_SEL_PORT_OFFS(x)	(0x4 * ((x) - 1))
+
 #define AM65_GMII_SEL_MODE_MII		0
 #define AM65_GMII_SEL_MODE_RMII		1
 #define AM65_GMII_SEL_MODE_RGMII	2
@@ -233,11 +235,12 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 				  phy_interface_t phy_mode, int slave)
 {
 	struct am65_cpsw_common	*common = priv->cpsw_common;
+	fdt_addr_t gmii_sel = common->gmii_sel + AM65_GMII_SEL_PORT_OFFS(slave);
 	u32 reg;
 	u32 mode = 0;
 	bool rgmii_id = false;
 
-	reg = readl(common->gmii_sel);
+	reg = readl(gmii_sel);
 
 	dev_dbg(common->dev, "old gmii_sel: %08x\n", reg);
 
@@ -273,9 +276,9 @@ static void am65_cpsw_gmii_sel_k3(struct am65_cpsw_priv *priv,
 	reg = mode;
 	dev_dbg(common->dev, "gmii_sel PHY mode: %u, new gmii_sel: %08x\n",
 		phy_mode, reg);
-	writel(reg, common->gmii_sel);
+	writel(reg, gmii_sel);
 
-	reg = readl(common->gmii_sel);
+	reg = readl(gmii_sel);
 	if (reg != mode)
 		dev_err(common->dev,
 			"gmii_sel PHY mode NOT SET!: requested: %08x, gmii_sel: %08x\n",