From: Tom Rini <trini@konsulko.com>
Date: Tue, 23 Apr 2024 14:33:37 +0000 (-0600)
Subject: Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon
X-Git-Tag: v2025.01-rc5-pxa1908~511
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=e78210231924bd28e13c3ed6fd647585117c3fdb;p=u-boot.git

Merge https://source.denx.de/u-boot/custodians/u-boot-snapdragon

Support is added for 5 new Qualcomm SoCs:

* QCM2290 and SM6115 are low and mid range SoCs used on the RB1 and RB2
  respectively. SM6115 is also used in some mid-range smartphones/tablets.
  Initial support includes buttons and USB (host and gadget).
* SM8250 is a flagship SoC from 2020 used on the RB5, as well as many flagship
  smartphones. The board can boot to a U-Boot prompt, but is missing regulators
  necessary for USB support.
* SM8550, and SM8650 are flagship mobile SoCs from 2023 and 2024
  respectively. Found on many high end smartphones.

In addition:

* Support is added for the Schneider HMIBSC board.
* mach-snapdragon switches to OF_UPSTREAM
* IPQ40xx gets several regressions fixed and some overall cleanup.
* The MSM serial driver gains the ability to generate the bit-clock
  automatically, no longer relying on a custom DT property.
* The Qualcomm SMMU driver gets a generic compatible (so per-SoC compatibles
  don't need to be added).
* Support for the GENI I2C controller is added.
* The qcom SPMI driver has SPMI v5 support fixed, and v7 support added.
* The qcom sdhci driver gets some fixes for SDCC v5 support.
* SDM845 gains sdcard support
* Support is added for the Synopsys eUSB2 PHY driver (used on SM8550 and SM8650)
* SYS_INIT_SP_BSS_OFFSET is set to 1.5M to give us more space for FDTs.
* RB2 gets a work-around to fix the USB dr_mode property before booting Linux.
---

e78210231924bd28e13c3ed6fd647585117c3fdb
diff --cc drivers/pinctrl/qcom/pinctrl-sm8550.c
index 0000000000,d9a8a65211..7265cb7340
mode 000000,100644..100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8550.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8550.c
@@@ -1,0 -1,75 +1,74 @@@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Qualcomm sm8550 pinctrl
+  *
+  * (C) Copyright 2024 Linaro Ltd.
+  *
+  */
+ 
 -#include <common.h>
+ #include <dm.h>
+ 
+ #include "pinctrl-qcom.h"
+ 
+ #define MAX_PIN_NAME_LEN 32
+ static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+ 
+ static const struct pinctrl_function msm_pinctrl_functions[] = {
+ 	{"qup1_se7", 1},
+ 	{"gpio", 0},
+ };
+ 
+ static const char *sm8550_get_function_name(struct udevice *dev,
+ 						 unsigned int selector)
+ {
+ 	return msm_pinctrl_functions[selector].name;
+ }
+ 
+ static const char *sm8550_get_pin_name(struct udevice *dev,
+ 					unsigned int selector)
+ {
+ 	static const char *special_pins_names[] = {
+ 		"ufs_reset",
+ 		"sdc2_clk",
+ 		"sdc2_cmd",
+ 		"sdc2_data",
+ 	};
+ 
+ 	if (selector >= 210 && selector <= 213)
+ 		snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
+ 	else
+ 		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ 
+ 	return pin_name;
+ }
+ 
+ static unsigned int sm8550_get_function_mux(__maybe_unused unsigned int pin,
+ 					    unsigned int selector)
+ {
+ 	return msm_pinctrl_functions[selector].val;
+ }
+ 
+ static struct msm_pinctrl_data sm8550_data = {
+ 	.pin_data = {
+ 		.pin_count = 214,
+ 		.special_pins_start = 210,
+ 	},
+ 	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ 	.get_function_name = sm8550_get_function_name,
+ 	.get_function_mux = sm8550_get_function_mux,
+ 	.get_pin_name = sm8550_get_pin_name,
+ };
+ 
+ static const struct udevice_id msm_pinctrl_ids[] = {
+ 	{ .compatible = "qcom,sm8550-tlmm", .data = (ulong)&sm8550_data },
+ 	{ /* Sentinel */ }
+ };
+ 
+ U_BOOT_DRIVER(pinctrl_sm8550) = {
+ 	.name		= "pinctrl_sm8550",
+ 	.id		= UCLASS_NOP,
+ 	.of_match	= msm_pinctrl_ids,
+ 	.ops		= &msm_pinctrl_ops,
+ 	.bind		= msm_pinctrl_bind,
+ };
+ 
diff --cc drivers/pinctrl/qcom/pinctrl-sm8650.c
index 0000000000,932132fa4a..d6cc1bbdda
mode 000000,100644..100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8650.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8650.c
@@@ -1,0 -1,75 +1,74 @@@
+ // SPDX-License-Identifier: GPL-2.0+
+ /*
+  * Qualcomm sm8650 pinctrl
+  *
+  * (C) Copyright 2024 Linaro Ltd.
+  *
+  */
+ 
 -#include <common.h>
+ #include <dm.h>
+ 
+ #include "pinctrl-qcom.h"
+ 
+ #define MAX_PIN_NAME_LEN 32
+ static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+ 
+ static const struct pinctrl_function msm_pinctrl_functions[] = {
+ 	{"qup2_se7", 1},
+ 	{"gpio", 0},
+ };
+ 
+ static const char *sm8650_get_function_name(struct udevice *dev,
+ 						 unsigned int selector)
+ {
+ 	return msm_pinctrl_functions[selector].name;
+ }
+ 
+ static const char *sm8650_get_pin_name(struct udevice *dev,
+ 					unsigned int selector)
+ {
+ 	static const char *special_pins_names[] = {
+ 		"ufs_reset",
+ 		"sdc2_clk",
+ 		"sdc2_cmd",
+ 		"sdc2_data",
+ 	};
+ 
+ 	if (selector >= 210 && selector <= 213)
+ 		snprintf(pin_name, MAX_PIN_NAME_LEN, special_pins_names[selector - 210]);
+ 	else
+ 		snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
+ 
+ 	return pin_name;
+ }
+ 
+ static unsigned int sm8650_get_function_mux(__maybe_unused unsigned int pin,
+ 					    unsigned int selector)
+ {
+ 	return msm_pinctrl_functions[selector].val;
+ }
+ 
+ static struct msm_pinctrl_data sm8650_data = {
+ 	.pin_data = {
+ 		.pin_count = 214,
+ 		.special_pins_start = 210,
+ 	},
+ 	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+ 	.get_function_name = sm8650_get_function_name,
+ 	.get_function_mux = sm8650_get_function_mux,
+ 	.get_pin_name = sm8650_get_pin_name,
+ };
+ 
+ static const struct udevice_id msm_pinctrl_ids[] = {
+ 	{ .compatible = "qcom,sm8650-tlmm", .data = (ulong)&sm8650_data },
+ 	{ /* Sentinel */ }
+ };
+ 
+ U_BOOT_DRIVER(pinctrl_sm8650) = {
+ 	.name		= "pinctrl_sm8650",
+ 	.id		= UCLASS_NOP,
+ 	.of_match	= msm_pinctrl_ids,
+ 	.ops		= &msm_pinctrl_ops,
+ 	.bind		= msm_pinctrl_bind,
+ };
+