From: Michal Simek <michal.simek@xilinx.com>
Date: Wed, 11 May 2022 09:52:52 +0000 (+0200)
Subject: arm64: zynqmp: Add PHY description for SGMII on vck190 SC
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=e4f1d2881e14145c29d5d8c05896e5bc73a15038;p=u-boot.git

arm64: zynqmp: Add PHY description for SGMII on vck190 SC

SGMII requires phy to be configured. The support for this has been added to
Linux and U-Boot already that's why also describe the phy via DT. Clock is
coming from si5332 chip (output 1) 125MHz which is only one GT line use on
this board.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/8ad8d0c2fc9690cc90f95feddf87b0e94a685a43.1652262769.git.michal.simek@amd.com
---

diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index f229880a70..7261837823 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -42,6 +42,12 @@
 		reg = <0x0 0x0 0x0 0x80000000>;
 	};
 
+	si5332_1: si5332_1 { /* u142 - GEM0 */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;
+	};
+
 	ina226-vccint {
 		compatible = "iio-hwmon";
 		io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
@@ -135,8 +141,17 @@
 	xlnx,mio-bank = <1>;
 };
 
+/* GEM SGMII */
+&psgtr {
+	status = "okay";
+	/* gem0 */
+	clocks = <&si5332_1>;
+	clock-names = "ref0";
+};
+
 &gem0 {
 	status = "okay";
+	phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
 	phy-handle = <&phy0>;
 	phy-mode = "sgmii";
 	is-internal-pcspma;