From: Tom Rini <trini@konsulko.com>
Date: Tue, 14 Dec 2021 18:36:39 +0000 (-0500)
Subject: CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=e4c3ce7e2845d75dc1696b2875bb632993a9c51c;p=u-boot.git

CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()

This CONFIG option is used in one of two ways.  The first way is that it
is defined to a static value, of an unsigned long size.  The second way
is that it is defined to something, typically a function, to determine
this value at run time.

However, in a few cases that function returns a static value.  Change
that to using the static value directly.

In the case of using something at run time, convert everything to using
a function of the same name and prototype.  This will allow for further
cleanups.

Finally, we have a few cases where the function is just not used, so
drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
---

diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c
index aefd21dc45..439d2e2b4d 100644
--- a/arch/arm/mach-davinci/cpu.c
+++ b/arch/arm/mach-davinci/cpu.c
@@ -91,3 +91,8 @@ int set_cpu_clk_info(void)
 	gd->bd->bi_dsp_freq = 0;
 	return 0;
 }
+
+unsigned long get_board_sys_clk(void)
+{
+	return clk_get(DAVINCI_ARM_CLKID);
+}
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index c26793d76c..d30940d7c3 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -49,7 +49,7 @@ int checkboard(void)
 	return 0;
 }
 
-int board_postclk_init(void)
+unsigned long get_board_sys_clk(void)
 {
 	/*
 	 * Obtain CPU clock frequency from board and cache in global
@@ -58,11 +58,17 @@ int board_postclk_init(void)
 	 */
 
 #ifdef CONFIG_SYS_FPGAREG_FREQ
-	gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+	return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
 #else
 	/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
-	gd->cpu_clk = 50000000UL;
+	return 50000000;
 #endif
+}
+
+int board_postclk_init(void)
+{
+	gd->cpu_clk = get_board_sys_clk();
+
 	return 0;
 }
 
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 7e7394f333..b14abac9a1 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -37,7 +37,7 @@ get_board_version(void)
 
 
 unsigned long
-get_clock_freq(void)
+get_board_sys_clk(void)
 {
 	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
 
diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h
index ddc2bb6c1f..fb74e8f6db 100644
--- a/board/freescale/common/cadmus.h
+++ b/board/freescale/common/cadmus.h
@@ -19,7 +19,7 @@ extern unsigned int get_board_version(void);
 /*
  * Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
  */
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
 
 
 /*
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index fbbd27d9d7..0647622cde 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -102,6 +102,7 @@ int checkboard(void)
 	return 0;
 }
 
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
 unsigned long get_board_sys_clk(void)
 {
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@@ -126,6 +127,7 @@ unsigned long get_board_sys_clk(void)
 	}
 	return 66666666;
 }
+#endif
 
 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 unsigned long get_board_ddr_clk(void)
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 73c2077ecd..8a112a699a 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -374,6 +374,7 @@ bool if_board_diff_clk(void)
 #endif
 }
 
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
 unsigned long get_board_sys_clk(void)
 {
 	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@@ -397,6 +398,7 @@ unsigned long get_board_sys_clk(void)
 
 	return 66666666;
 }
+#endif
 
 #ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 unsigned long get_board_ddr_clk(void)
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 4ece1e6ea0..894fe8ee27 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -148,7 +148,7 @@ int board_early_init_r(void)
 	return 0;
 }
 
-unsigned long get_board_sys_clk(unsigned long dummy)
+unsigned long get_board_sys_clk(void)
 {
 	u8 sysclk_conf = CPLD_READ(sysclk_sw1);
 
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index ac373d7724..7f59172076 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
 	return CONFIG_SYS_L3_SIZE;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 #if defined(CONFIG_SPL_MMC_BOOT)
 #define GPIO1_SD_SEL 0x00020000
 int board_mmc_getcd(struct mmc *mmc)
@@ -74,7 +69,7 @@ void board_init_f(ulong bootflag)
 #endif
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
+	sys_clk = CONFIG_SYS_CLK_FREQ;
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index ab7675e209..539a5c7344 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -162,11 +162,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 #ifdef CONFIG_TARGET_T1024RDB
 void board_reset(void)
 {
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index c7df11100e..6acc5161b6 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
 	return CONFIG_SYS_L3_SIZE;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 #define FSL_CORENET_CCSR_PORSR1_RCW_MASK	0xFF800000
 void board_init_f(ulong bootflag)
 {
@@ -73,7 +68,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
+	sys_clk = CONFIG_SYS_CLK_FREQ;
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	uart_clk = sys_clk * plat_ratio / 2;
 
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 2204a98ac8..40aa0c5df3 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -24,11 +24,6 @@ phys_size_t get_effective_memsize(void)
 	return CONFIG_SYS_L3_SIZE;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
@@ -43,7 +38,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
+	sys_clk = CONFIG_SYS_CLK_FREQ;
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 3611dbbf32..1c8017b593 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -109,11 +109,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 int misc_init_r(void)
 {
 	u8 reg;
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 69d1449b07..8c7421da81 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -30,11 +30,6 @@ phys_size_t get_effective_memsize(void)
 	return CONFIG_SYS_L3_SIZE;
 }
 
-unsigned long get_board_sys_clk(void)
-{
-	return CONFIG_SYS_CLK_FREQ;
-}
-
 void board_init_f(ulong bootflag)
 {
 	u32 plat_ratio, sys_clk, ccb_clk;
@@ -52,7 +47,7 @@ void board_init_f(ulong bootflag)
 	console_init_f();
 
 	/* initialize selected port with appropriate baud rate */
-	sys_clk = get_board_sys_clk();
+	sys_clk = CONFIG_SYS_CLK_FREQ;
 	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	ccb_clk = sys_clk * plat_ratio / 2;
 
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 4f5164e63c..ca24b960c7 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -181,11 +181,6 @@ unsigned long get_serial_clock(unsigned long dummy)
 	return (gd->bus_clk / 2);
 }
 
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
-	return 66666666;
-}
-
 int misc_init_f(void)
 {
 	/* configure QRIO pis for i2c deblocking */
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 8ca65ca859..8c72c15445 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -9,7 +9,7 @@
 /*
  * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
  */
-unsigned long get_board_sys_clk(ulong dummy)
+unsigned long get_board_sys_clk(void)
 {
 #if defined(CONFIG_MPC85xx)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -33,13 +33,13 @@ unsigned long get_board_sys_clk(ulong dummy)
  * Return DDR input clock - synchronous with SYSCLK or 66 MHz
  * Note: 86xx doesn't support asynchronous DDR clk
  */
-unsigned long get_board_ddr_clk(ulong dummy)
+unsigned long get_board_ddr_clk(void)
 {
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
 
 	if (ddr_ratio == 0x7)
-		return get_board_sys_clk(dummy);
+		return get_board_sys_clk();
 
 #ifdef CONFIG_ARCH_P2020
 	if (in_be32(&gur->gpporcr) & 0x20000)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index c5cefd4741..5c1d9b522e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -24,9 +24,9 @@
 
 #ifndef __ASSEMBLY__
 #include <linux/stringify.h>
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
 #endif
-#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index d5f1ffe371..424dd72d2e 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -49,10 +49,10 @@
 #endif
 
 #ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
+unsigned long get_board_sys_clk(void);
 #include <linux/stringify.h>
 #endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0)
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
 
 /*
  * These can be toggled for performance analysis, otherwise use default.
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 7bd46c41df..aecf2452ad 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -115,10 +115,6 @@
 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 #endif
 
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
 #define CONFIG_SYS_CLK_FREQ	100000000
 
 /*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 5815bd4c36..e90b30db52 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -88,10 +88,6 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
 
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
 #define CONFIG_SYS_CLK_FREQ	66660000
 
 /*
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index fc8c33ac57..037425bba1 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -226,10 +226,6 @@
 
 #define CONFIG_SYS_CLK_FREQ	66666666
 
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
 /*
  * DDR Setup
  */
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 8456a6b2c3..079d2d7194 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -34,8 +34,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"	\
diff --git a/include/configs/blanche.h b/include/configs/blanche.h
index f048f158ed..f2cc765b96 100644
--- a/include/configs/blanche.h
+++ b/include/configs/blanche.h
@@ -45,8 +45,7 @@
 #endif
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 /* ENV setting */
 
diff --git a/include/configs/condor.h b/include/configs/condor.h
index 36466f0f50..429047b112 100644
--- a/include/configs/condor.h
+++ b/include/configs/condor.h
@@ -27,7 +27,7 @@
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ	33333333u
+#define CONFIG_SYS_CLK_FREQ	33333333
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 9d27e50229..d1c0cc2363 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -17,8 +17,11 @@
 /*
  * SoC Configuration
  */
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
diff --git a/include/configs/eagle.h b/include/configs/eagle.h
index ee53504250..6d17b065fe 100644
--- a/include/configs/eagle.h
+++ b/include/configs/eagle.h
@@ -18,7 +18,7 @@
 
 /* Board Clock */
 /* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ	33333333u
+#define CONFIG_SYS_CLK_FREQ	33333333
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
diff --git a/include/configs/falcon.h b/include/configs/falcon.h
index d783faf180..f9c3c2b9c7 100644
--- a/include/configs/falcon.h
+++ b/include/configs/falcon.h
@@ -26,7 +26,7 @@
 
 /* Board Clock */
 /* XTAL_CLK : 16.66MHz */
-#define CONFIG_SYS_CLK_FREQ	16666666u
+#define CONFIG_SYS_CLK_FREQ	16666666
 
 /* Generic Timer Definitions (use in assembler source) */
 #define COUNTER_FREQUENCY	0xFE502A	/* 16.66MHz from CPclk */
diff --git a/include/configs/gose.h b/include/configs/gose.h
index 60a89e0023..2e35752664 100644
--- a/include/configs/gose.h
+++ b/include/configs/gose.h
@@ -30,8 +30,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 65a38c5757..18a1ebd456 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -30,8 +30,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/lager.h b/include/configs/lager.h
index c5001e3ec7..6e003e8466 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -31,8 +31,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h
index 0e4d134dbd..21ba9b8da8 100644
--- a/include/configs/legoev3.h
+++ b/include/configs/legoev3.h
@@ -17,8 +17,11 @@
 /*
  * SoC Configuration
  */
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index bc707ebfdc..1036a05a29 100644
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -17,7 +17,10 @@
 /*
  * SoC Configuration
  */
-#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 #define CONFIG_SYS_OSCIN_FREQ		24000000
 #define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
diff --git a/include/configs/porter.h b/include/configs/porter.h
index 7ffcf5fc38..da2e171e00 100644
--- a/include/configs/porter.h
+++ b/include/configs/porter.h
@@ -35,8 +35,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/silk.h b/include/configs/silk.h
index eee60fdfab..785caa7b89 100644
--- a/include/configs/silk.h
+++ b/include/configs/silk.h
@@ -35,8 +35,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/stout.h b/include/configs/stout.h
index a1e7e86f39..0d077ea031 100644
--- a/include/configs/stout.h
+++ b/include/configs/stout.h
@@ -39,8 +39,7 @@
 #define CONFIG_BITBANGMII_MULTI
 
 /* Board Clock */
-#define RMOBILE_XTAL_CLK	20000000u
-#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ	20000000
 
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootm_size=0x10000000\0"
diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h
index ccc90a66f7..d1ba78a030 100644
--- a/include/configs/xtfpga.h
+++ b/include/configs/xtfpga.h
@@ -23,7 +23,10 @@
 #define CONFIG_XTFPGA
 
 /* FPGA CPU freq after init */
-#define CONFIG_SYS_CLK_FREQ		(gd->cpu_clk)
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ		get_board_sys_clk()
 
 /*===================*/
 /* RAM Layout        */