From: Wolfgang Denk <wd@pollux.denx.de>
Date: Thu, 18 Aug 2005 22:36:45 +0000 (+0200)
Subject: Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=df3c7c8f52473297e4049efd8309d3ea944606f7;p=u-boot.git

Change main clock on CMC-PU2 board from 207 MHz to 179 MHz
because of a bug in the AT91RM9200 CPU PLL
Patch by Martin Krause, 22 Apr 2005
---

diff --git a/CHANGELOG b/CHANGELOG
index 56f353997b..cf0dec01a3 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,10 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Change main clock on CMC-PU2 board from 207 MHz to 179 MHz 
+  because of a bug in the AT91RM9200 CPU PLL
+  Patch by Martin Krause, 22 Apr 2005
+
 * Add automatic HW detection for another CMC_PU2 variant
   Patch by Martin Krause, 20 Apr 2005
 
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index 3554355426..9ed538b110 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -26,7 +26,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91C_MAIN_CLOCK	207360000	/* from 18.432 MHz crystal (18432000 / 4 * 45) */
+#define AT91C_MAIN_CLOCK	179712000	/* from 18.432 MHz crystal (18432000 / 4 * 39) */
 #define AT91C_MASTER_CLOCK	(AT91C_MAIN_CLOCK/3)	/* peripheral clock */
 
 #define AT91_SLOW_CLOCK		32768	/* slow clock */
@@ -53,7 +53,7 @@
 #define SMC2_CSR_VAL	0x100032ad /* 16bit, 2 TDF, 4 WS */
 
 /* clocks */
-#define PLLAR_VAL	0x202CBE04 /* 207.360 MHz for PCK */
+#define PLLAR_VAL	0x2026BE04 /* 179,712 MHz for PCK */
 #define PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
 #define MCKR_VAL	0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */