From: Marek Behún Date: Tue, 24 Apr 2018 15:21:19 +0000 (+0200) Subject: phy: marvell: a3700: Set USB3 RX wait depending on ref clock X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=de49bd0e73f7d4e764f3c6b67a536de5d4e8841b;p=u-boot.git phy: marvell: a3700: Set USB3 RX wait depending on ref clock According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 4fb23bb547..3da9eedc23 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -382,20 +382,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 3. Check crystal jumper setting and program the Power and PLL * Control accordingly + * 4. Change RX wait */ if (get_ref_clk() == 40) { /* 40 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane); + usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); } else { /* 25 MHz */ usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane); + usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane); } - /* - * 4. Change RX wait - */ - usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane); - /* * 5. Enable idle sync */