From: Kever Yang Date: Tue, 28 Nov 2017 08:04:16 +0000 (+0800) Subject: rockchip: rk3128: add soc basic support X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=daeed1dbb5026de081298d1e39c290625d71f137;p=u-boot.git rockchip: rk3128: add soc basic support RK3128 is a SoC from Rockchip with quad-core Cortex-A7 CPU and mali400 GPU. Support Nand flash, eMMC, SD card, USB 2.0 host and device, HDMI/LVDS/MIPI display. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a26736a5ac..1e74db3607 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,15 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3128 + bool "Support Rockchip RK3128" + select CPU_V7 + help + The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3188 bool "Support Rockchip RK3188" select CPU_V7 @@ -211,6 +220,7 @@ config SPL_MMC_SUPPORT default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 7e1f864383..e1b0519b1f 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -30,6 +30,7 @@ ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-y += boot_mode.o obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o @@ -43,6 +44,7 @@ obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif diff --git a/arch/arm/mach-rockchip/rk3128-board.c b/arch/arm/mach-rockchip/rk3128-board.c new file mode 100644 index 0000000000..2e8393d70a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128-board.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +__weak int rk_board_late_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + setup_boot_mode(); + + return rk_board_late_init(); +} + +int board_init(void) +{ + int ret = 0; + + rockchip_timer_init(); + + ret = regulators_enable_boot_on(false); + if (ret) { + debug("%s: Cannot enable boot on regulator\n", __func__); + return ret; + } + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x8400000; + /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ + gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + + gd->bd->bi_dram[0].size + 0xe00000; + gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start + + gd->ram_size - gd->bd->bi_dram[1].start; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include +#include + +static struct dwc2_plat_otg_data rk3128_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3128-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3128-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3128_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + +#if defined(CONFIG_USB_FUNCTION_FASTBOOT) +int fb_set_reboot_flag(void) +{ + struct rk3128_grf *grf; + + printf("Setting reboot to fastboot flag ...\n"); + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Set boot mode to fastboot */ + writel(BOOT_FASTBOOT, &grf->os_reg[0]); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig new file mode 100644 index 0000000000..e69de29bb2 diff --git a/arch/arm/mach-rockchip/rk3128/Makefile b/arch/arm/mach-rockchip/rk3128/Makefile new file mode 100644 index 0000000000..0f63d921de --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2017 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3128.o +obj-y += syscon_rk3128.o diff --git a/arch/arm/mach-rockchip/rk3128/rk3128.c b/arch/arm/mach-rockchip/rk3128/rk3128.c new file mode 100644 index 0000000000..9d6e3b1ee1 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/rk3128.c @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +int arch_cpu_init(void) +{ + /* We do some SoC one time setting here. */ + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c new file mode 100644 index 0000000000..0b636390ac --- /dev/null +++ b/arch/arm/mach-rockchip/rk3128/syscon_rk3128.c @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id rk3128_syscon_ids[] = { + { .compatible = "rockchip,rk3128-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3128) = { + .name = "rk3128_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3128_syscon_ids, +}; diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h new file mode 100644 index 0000000000..e915a562b9 --- /dev/null +++ b/include/configs/rk3128_common.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3128_COMMON_H +#define __CONFIG_RK3128_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) + +#define CONFIG_SYS_NS16550_MEM32 + +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ + +/* MMC/SD IP block */ +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_SUPPORT_VFAT +#define CONFIG_FS_EXT4 + +/* RAW SD card / eMMC locations. */ +#define CONFIG_SYS_SPI_U_BOOT_OFFS (128 << 10) + +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define SDRAM_MAX_SIZE 0x80000000 + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 + +#ifndef CONFIG_SPL_BUILD + +/* usb mass storage */ +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60500000\0" \ + "pxefile_addr_r=0x60600000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + "partitions=" PARTS_DEFAULT \ + BOOTENV + +#endif + +#endif