From: Shengyu Qu <wiagn233@outlook.com>
Date: Wed, 9 Aug 2023 13:11:31 +0000 (+0800)
Subject: riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=d365f6646aa4ecaabc58c07ecc432a3177f13138;p=u-boot.git

riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE

Add a Kconfig item to allow SPL to clear stack/GD/malloc area before
using them.

Signed-off-by: Bo Gan <ganboing@gmail.com>
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 867cbcbe74..6771d8d919 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF
 	help
 	  Do not enable data cache in SPL.
 
+config SPL_ZERO_MEM_BEFORE_USE
+	bool "Zero memory before use"
+	depends on SPL
+	default n
+	help
+	  Zero stack/GD/malloc area in SPL before using them, this is needed for
+	  Sifive core devices that uses L2 cache to store SPL.
+
 # board-specific options below
 source "board/AndesTech/ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"