From: Lokesh Vutla <lokeshvutla@ti.com>
Date: Thu, 4 Jun 2015 04:38:50 +0000 (+0530)
Subject: ARM: DRA7: emif: Fix DDR init sequence during warm reset
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=c997da5c53586e0cb220d94179f922e865cffb62;p=u-boot.git

ARM: DRA7: emif: Fix DDR init sequence during warm reset

Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.

Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index ca22c00601..f5b22f6a78 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -1170,7 +1170,7 @@ static void do_sdram_init(u32 base)
 	 * Changing the timing registers in EMIF can happen(going from one
 	 * OPP to another)
 	 */
-	if (!(in_sdram || warm_reset())) {
+	if (!in_sdram && (!warm_reset() || is_dra7xx())) {
 		if (emif_sdram_type(regs->sdram_config) ==
 		    EMIF_SDRAM_TYPE_LPDDR2)
 			lpddr2_init(base, regs);
@@ -1178,7 +1178,7 @@ static void do_sdram_init(u32 base)
 			ddr3_init(base, regs);
 	}
 	if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
-	    EMIF_SDRAM_TYPE_DDR3)) {
+	    EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
 		omap5_ddr3_leveling(base, regs);