From: Jagan Teki <jagan@amarulasolutions.com>
Date: Tue, 6 Jun 2023 17:09:17 +0000 (+0530)
Subject: clk: rockchip: rk3328: Handle usb480m phy clock
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=c0165258582078c206faca352b0f63ccdf535ce7;p=u-boot.git

clk: rockchip: rk3328: Handle usb480m phy clock

Handle USB480M clock ID in set_rate() and set_parent()
to allow the dt assigned-clocks and assigned-clock-parents
work on rk3328.dtsi

Cc: Lukasz Majewski <lukma@denx.de>
Cc: Sean Anderson <seanga2@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c
index 969b7a8581..ef97381f0e 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -681,6 +681,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
 	case ACLK_GMAC:
 	case PCLK_GMAC:
 	case SCLK_USB3OTG_SUSPEND:
+	case USB480M:
 		return 0;
 	default:
 		return -ENOENT;
@@ -771,6 +772,7 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
 	case SCLK_MAC2IO_EXT:
 		return rk3328_gmac2io_ext_set_parent(clk, parent);
 	case DCLK_LCDC:
+	case USB480M:
 	case SCLK_PDM:
 	case SCLK_RTC32K:
 	case SCLK_UART0: