From: Yann Gautier Date: Tue, 13 Sep 2022 11:23:44 +0000 (+0200) Subject: mmc: stm32_sdmmc2: add dual data rate support X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=be1872982e425375a7da6ac75da946f9d15df405;p=u-boot.git mmc: stm32_sdmmc2: add dual data rate support To support dual data rate with STM32 sdmmc2 driver, the dedicated bit (DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass (no divider) is not allowed in this case. This is required for the eMMC DDR modes. Signed-off-by: Yann Gautier Reviewed-by: Jaehoon Chung --- diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 7ab4d949e7..952d02f9b8 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -598,13 +598,16 @@ static int stm32_sdmmc2_set_ios(struct udevice *dev) * clk_div > 0 and NEGEDGE = 1 => command and data generated on * SDMMCCLK falling edge */ - if (desired && ((sys_clock > desired) || + if (desired && (sys_clock > desired || mmc->ddr_mode || IS_RISING_EDGE(plat->clk_reg_msk))) { clk = DIV_ROUND_UP(sys_clock, 2 * desired); if (clk > SDMMC_CLKCR_CLKDIV_MAX) clk = SDMMC_CLKCR_CLKDIV_MAX; } + if (mmc->ddr_mode) + clk |= SDMMC_CLKCR_DDR; + if (mmc->bus_width == 4) clk |= SDMMC_CLKCR_WIDBUS_4; if (mmc->bus_width == 8)