From: Hou Zhiqiang Date: Tue, 20 Aug 2019 09:35:26 +0000 (+0000) Subject: powerpc: Enable device tree support for T1024RDB X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=bd74ea19089b8333fef2414b18b814ebe6fc176b;p=u-boot.git powerpc: Enable device tree support for T1024RDB Add device tree for T1024RDB board and enable CONFIG_OF_CONTROL so that device tree can be compiled. Update board README for device tree usage. Signed-off-by: Hou Zhiqiang Reviewed-by: Prabhakar Kushwaha --- diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 90023936bf..b7acba54e4 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb diff --git a/arch/powerpc/dts/e5500_power_isa.dtsi b/arch/powerpc/dts/e5500_power_isa.dtsi new file mode 100644 index 0000000000..0a0943b0bb --- /dev/null +++ b/arch/powerpc/dts/e5500_power_isa.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * e5500 Power ISA Device Tree Source (include) + * + * Copyright 2012 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/ { + cpus { + power-isa-version = "2.06"; + power-isa-b; // Base + power-isa-e; // Embedded + power-isa-atb; // Alternate Time Base + power-isa-cs; // Cache Specification + power-isa-ds; // Decorated Storage + power-isa-e.ed; // Embedded.Enhanced Debug + power-isa-e.pd; // Embedded.External PID + power-isa-e.hv; // Embedded.Hypervisor + power-isa-e.le; // Embedded.Little-Endian + power-isa-e.pm; // Embedded.Performance Monitor + power-isa-e.pc; // Embedded.Processor Control + power-isa-ecl; // Embedded Cache Locking + power-isa-exp; // External Proxy + power-isa-fp; // Floating Point + power-isa-fp.r; // Floating Point.Record + power-isa-mmc; // Memory Coherence + power-isa-scpm; // Store Conditional Page Mobility + power-isa-wt; // Wait + power-isa-64; // 64-bit + fsl,eref-deo; // Data Cache Extended Operations + mmu-type = "power-embedded"; + }; +}; diff --git a/arch/powerpc/dts/t1024rdb.dts b/arch/powerpc/dts/t1024rdb.dts new file mode 100644 index 0000000000..19a6652a23 --- /dev/null +++ b/arch/powerpc/dts/t1024rdb.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T1024RDB Device Tree Source + * + * Copyright 2013 - 2015 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/include/ "t102x.dtsi" + +/ { + model = "fsl,T1024RDB"; + compatible = "fsl,T1024RDB"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; +}; diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi new file mode 100644 index 0000000000..2393e316f8 --- /dev/null +++ b/arch/powerpc/dts/t102x.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * T102X Silicon/SoC Device Tree Source (pre include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2019 NXP + */ + +/dts-v1/; + +/include/ "e5500_power_isa.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: PowerPC,e5500@0 { + device_type = "cpu"; + reg = <0>; + #cooling-cells = <2>; + }; + cpu1: PowerPC,e5500@1 { + device_type = "cpu"; + reg = <1>; + #cooling-cells = <2>; + }; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + + mpic: pic@40000 { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <4>; + reg = <0x40000 0x40000>; + compatible = "fsl,mpic", "chrp,open-pic"; + device_type = "open-pic"; + clock-frequency = <0x0>; + }; + }; +}; diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index a0af25a432..dde3f8ca37 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -251,6 +251,25 @@ Software configurations and board settings SW3[3] = '0' for eMMC (or 'switch emmc' by software) +device tree support and how to enable it for different configs +-------------------------------------------------------------- +device tree support is available for t1024rdb for below mentioned boot, +1. nor boot +2. nand boot +3. sd boot +4. spiflash boot + +to enable device tree support for other boot, below configs need to be +enabled in relative defconfig file, +1. config_default_device_tree="t1024rdb" (change default device tree name if required) +2. config_of_control +3. config_mpc85xx_have_reset_vector if reset vector is located at + config_reset_vector_address - 0xffc + +if device tree support is enabled in defconfig, +1. use 'u-boot-with-dtb.bin' for nor boot. +2. use 'u-boot-with-spl-pbl.bin' for other boot. + 2-stage NAND/SPI/SD boot loader ------------------------------- PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM. diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index dec004462b..27ed0e7b8c 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -45,6 +45,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_NAND=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -70,4 +72,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 5143046862..010b49c705 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -43,6 +43,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_MMC=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -67,4 +69,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index ff45291668..ff267fc32a 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -44,6 +44,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -68,4 +70,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 9059329450..a781738801 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -2,6 +2,7 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_MPC85xx=y CONFIG_TARGET_T1024RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y @@ -29,6 +30,8 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_IS_IN_FLASH=y CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y @@ -53,4 +56,3 @@ CONFIG_SPI=y CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y