From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 31 May 2009 12:53:18 +0000 (+0200) Subject: at91: move cpu info print to cpu X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=b2403589b4d9996394bafc73eca3623f43ac2c31;p=u-boot.git at91: move cpu info print to cpu Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index d24ef9a76e..d2598a0680 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -382,15 +382,8 @@ int board_eth_init(bd_t *bis) int checkboard (void) { char *ss; - char buf[32]; printf ("Board : Ronetix PM9263\n"); - printf ("Crystal frequency: %8s MHz\n", - strmhz(buf, get_main_clk_rate())); - printf ("CPU clock : %8s MHz\n", - strmhz(buf, get_cpu_clk_rate())); - printf ("Master clock : %8s MHz\n", - strmhz(buf, get_mck_clk_rate())); switch (gd->fb_base) { case PHYS_PSRAM: diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index 2ae97fe497..f2f7b62550 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -21,17 +21,34 @@ * MA 02111-1307 USA */ -#include +#include #include #include #include #include +#ifndef AT91_MAIN_CLOCK +#define AT91_MAIN_CLOCK 0 +#endif + int arch_cpu_init(void) { -#ifdef AT91_MAIN_CLOCK return at91_clock_init(AT91_MAIN_CLOCK); -#else - return at91_clock_init(0); -#endif } + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU: %s\n", AT91_CPU_NAME); + printf("Crystal frequency: %8s MHz\n", + strmhz(buf, get_main_clk_rate())); + printf("CPU clock : %8s MHz\n", + strmhz(buf, get_cpu_clk_rate())); + printf("Master clock : %8s MHz\n", + strmhz(buf, get_mck_clk_rate())); + + return 0; +} +#endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index d60c417a11..f0dbe81d14 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -29,6 +29,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 15