From: Albert ARIBAUD <albert.u.boot@aribaud.net>
Date: Mon, 28 Jul 2014 10:26:21 +0000 (+0200)
Subject: Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=b1cdd8baa14f518288ceddb391d6587c1ecb3174;p=u-boot.git

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
---

b1cdd8baa14f518288ceddb391d6587c1ecb3174
diff --cc board/ti/am43xx/board.c
index 7e239f1c88,f6577769e7..51fa9e04a3
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@@ -605,46 -485,23 +606,59 @@@ void sdram_init(void
  }
  #endif
  
+ /* setup board specific PMIC */
+ int power_init_board(void)
+ {
+ 	struct pmic *p;
+ 
+ 	power_tps65218_init(I2C_PMIC);
+ 	p = pmic_get("TPS65218_PMIC");
+ 	if (p && !pmic_probe(p))
+ 		puts("PMIC:  TPS65218\n");
+ 
+ 	return 0;
+ }
+ 
  int board_init(void)
  {
 +	struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
 +	u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
 +	    modena_init0_bw_integer, modena_init0_watermark_0;
 +
  	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  
 +	/* Clear all important bits for DSS errata that may need to be tweaked*/
 +	mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
 +	                   MREQPRIO_0_SAB_INIT0_MASK;
 +
 +	mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
 +
 +	modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
 +	                                   BW_LIMITER_BW_FRAC_MASK;
 +
 +	modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
 +	                                BW_LIMITER_BW_INT_MASK;
 +
 +	modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
 +	                                 BW_LIMITER_BW_WATERMARK_MASK;
 +
 +	/* Setting MReq Priority of the DSS*/
 +	mreqprio_0 |= 0x77;
 +
 +	/*
 +	 * Set L3 Fast Configuration Register
 +	 * Limiting bandwith for ARM core to 700 MBPS
 +	 */
 +	modena_init0_bw_fractional |= 0x10;
 +	modena_init0_bw_integer |= 0x3;
 +
 +	writel(mreqprio_0, &cdev->mreqprio_0);
 +	writel(mreqprio_1, &cdev->mreqprio_1);
 +
 +	writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
 +	writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
 +	writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
 +
  	return 0;
  }