From: Andy Yan <andy.yan@rock-chips.com>
Date: Tue, 26 Nov 2019 13:15:39 +0000 (+0800)
Subject: rockchip: px5: enable spl-fifo-mode for emmc for px5-evb
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=afe18f205e269682edd680cb4a5bcbe2094ea58b;p=u-boot.git

rockchip: px5: enable spl-fifo-mode for emmc for px5-evb

We need load some parts of ATF to sram, but rockchip
dwmmc controllers can't do dma to non-ddr addresses
space, so set the mmc controller into fifo mode in spl.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
---

diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
index 002767a033..936ce55727 100644
--- a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
+++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi
@@ -58,6 +58,8 @@
 };
 
 &emmc {
+	/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
+	u-boot,spl-fifo-mode;
 	u-boot,dm-pre-reloc;
 };