From: Jeffrey Mann <mannj@embeddedplanet.com>
Date: Wed, 16 May 2007 11:23:10 +0000 (+0200)
Subject: [PATCH] Run new sequoia boards with an EBC speed of 83MHz
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=ada4697d;p=u-boot.git

[PATCH] Run new sequoia boards with an EBC speed of 83MHz

Because the Sequoia board does not boot with an EBC faster than 66MHz,
the clock divider are changed after the initial boot process.

This allows for maximum clocking speeds  to be achieved on newer boards.
Sequoia boards with 666.66 MHz processors require that the EBC divider
be set to 3 in order to start the initial boot process at a slower EBC
speed. After the initial boot process, the divider can be set back to 2,
which will cause the boards to run at 83.333MHz. This is backward
compatible with boards with 533.33 MHz processors, as these boards will
already be set with an EBC divider of 2.

Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
---

diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 930fa71cb9..870401458e 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -132,6 +132,12 @@ int board_early_init_f(void)
 		(0x80000000 >> (28 + CFG_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
+	/* Update EBC speed after booting from i2c bootstrap settings
+	 * on newer boards with 33.333 MHZ Clocks
+	 */
+	if (in8(CFG_BCSR_BASE + 3) & 0x80)
+		mtcpr(0xe0, 0x02000000);
+
 	return 0;
 }
 
@@ -363,8 +369,8 @@ int checkboard(void)
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = *(u8 *)(CFG_BCSR_BASE + 0);
-	val = *(u8 *)(CFG_BCSR_BASE + 5) & 0x01;
+	rev = in8(CFG_BCSR_BASE + 0);
+	val = in8(CFG_BCSR_BASE + 5) & 0x01;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {