From: Rick Chen <rick@andestech.com>
Date: Thu, 29 Aug 2019 02:30:13 +0000 (+0800)
Subject: riscv: ax25: add imply v5l2 cache controller
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a8323d1816c978c012ea2fbbc844f0cbd5c82bdc;p=u-boot.git

riscv: ax25: add imply v5l2 cache controller

Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index f4b59cb71d..d411a79c21 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -6,6 +6,7 @@ config RISCV_NDS
 	imply RISCV_TIMER
 	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
 	imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
+	imply V5L2_CACHE
 	help
 	  Run U-Boot on AndeStar V5 platforms and use some specific features
 	  which are provided by Andes Technology AndeStar V5 families.