From: Marek Vasut Date: Mon, 6 Mar 2023 14:53:46 +0000 (+0100) Subject: net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a79de0808a8dc738ec2076ad47d431c64452111e;p=u-boot.git net: dwc_eth_qos: Set DMA_MODE SWR bit to reset the MAC The driver currently only waits for DMA_MODE SWR bit to clear itself. This is insufficient e.g. on i.MX8M Plus, where the MAC must be reset before IOMUX GPR[1] content is latched into the MAC and used. Without the proper reset, the i.MX8M Plus MAC variant does not take the value in IOMUX GPR[1] into account, which makes it impossible e.g. to switch interface mode from RGMII to any other. Since proper reset is desired in general to put the block into defined state, always assert the DMA_MODE SWR bit before waiting for the bit to clear itself. Reviewed-by: Ramon Fried Signed-off-by: Marek Vasut --- diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index 9a5575e7b8..ec58697b31 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -761,6 +761,12 @@ static int eqos_start(struct udevice *dev) eqos->reg_access_ok = true; + /* + * Assert the SWR first, the actually reset the MAC and to latch in + * e.g. i.MX8M Plus GPR[1] content, which selects interface mode. + */ + setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR); + ret = wait_for_bit_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR, false, eqos->config->swr_wait, false);