From: Stefan Agner <stefan.agner@toradex.com>
Date: Tue, 26 Jun 2018 09:10:52 +0000 (+0200)
Subject: colibri_imx7: improve DDR3 timing
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a19797b22cbc955ade2ef59c78fbdeea866285a9;p=u-boot.git

colibri_imx7: improve DDR3 timing

This makes sure that all Colibri iMX7 modules work with the
same timing. The changes are:
- Disable ODT on read (JEDEC standard JESD79-3F says in chapter
  5.2.3 ODT during Reads: "As the DDR3 SDRAM can not terminate
  and drive at the same time, RTT must be disabled at least half
  a clock cycle..." and also MX7D SABRESD is disabling it)
  This alone fixed memory issues for two Colibri iMX7 1GB modules
  which showed issues before
- Make sure tRFC(min) is at least 260ns
- Make sure tRC is >50.625ns
- tRP needs to be >13.125ns, we can lower from 18.75ns to 15ns
- tFAW is not relevant, leave at reset

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
---

diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg
index 1d66884df4..25cfd5c6f8 100644
--- a/board/toradex/colibri_imx7/imximage.cfg
+++ b/board/toradex/colibri_imx7/imximage.cfg
@@ -57,7 +57,7 @@ DATA 4 0x307a01a4 0x00100020
 /* DDRC_DFIUPD2 */
 DATA 4 0x307a01a8 0x80100004
 /* DDRC_RFSHTMG */
-DATA 4 0x307a0064 0x00400045
+DATA 4 0x307a0064 0x00400046
 /* DDRC_MP_PCTRL_0 */
 DATA 4 0x307a0490 0x00000001
 /* DDRC_INIT0 */
@@ -73,15 +73,15 @@ DATA 4 0x307a00e4 0x00100004
 /* DDRC_RANKCTL */
 DATA 4 0x307a00f4 0x0000033f
 /* DDRC_DRAMTMG0 */
-DATA 4 0x307a0100 0x090b090a
+DATA 4 0x307a0100 0x0910090a
 /* DDRC_DRAMTMG1 */
-DATA 4 0x307a0104 0x000d020d
+DATA 4 0x307a0104 0x000d020e
 /* DDRC_DRAMTMG2 */
 DATA 4 0x307a0108 0x03040307
 /* DDRC_DRAMTMG3 */
 DATA 4 0x307a010c 0x00002006
 /* DDRC_DRAMTMG4 */
-DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0110 0x04020204
 /* DDRC_DRAMTMG5 */
 DATA 4 0x307a0114 0x03030202
 /* DDRC_DRAMTMG8 */
@@ -105,7 +105,7 @@ DATA 4 0x307a0218 0x07070707
 /* DDRC_ODTCFG */
 DATA 4 0x307a0240 0x06000601
 /* DDRC_ODTMAP */
-DATA 4 0x307a0244 0x00000011
+DATA 4 0x307a0244 0x00000001
 /* SRC_DDRC_RCR */
 DATA 4 0x30391000 0x00000000
 /* DDR_PHY_PHY_CON0 */