From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Date: Tue, 27 Aug 2019 11:05:06 +0000 (+0000)
Subject: P5040: dts: Added PCIe DT nodes
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=a1958b118b481d148908bf7c41e51a8249e76fab;p=u-boot.git

P5040: dts: Added PCIe DT nodes

P5040 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 2.0, and this
patch is to add DT node for each PCIe controller.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
---

diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi
index b6f6c5dd58..8ab123dca4 100644
--- a/arch/powerpc/dts/p5040.dtsi
+++ b/arch/powerpc/dts/p5040.dtsi
@@ -59,4 +59,40 @@
 			clock-frequency = <0x0>;
 		};
 	};
+
+	pcie@ffe200000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <0>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe201000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <1>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
+
+	pcie@ffe202000 {
+		compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
+		reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
+		law_trgt_if = <2>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		bus-range = <0x0 0xff>;
+		ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
+			  0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
+	};
 };