From: Benjamin Hahn <B.Hahn@phytec.de>
Date: Tue, 28 May 2024 13:35:15 +0000 (+0200)
Subject: board: phycore_imx8mp: enable setting 2GHz timings without RAM size
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=95cf918f16ddaf7e6e4b1b4dfacecb9d9609d6f7;p=u-boot.git

board: phycore_imx8mp: enable setting 2GHz timings without RAM size

make it possible to set the RAM timing frequency statically independent
from the RAM size. Fixed RAM timing frequency can be used while the
RAM size is still determined by the EEPROM image.

Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
---

diff --git a/board/phytec/phycore_imx8mp/Kconfig b/board/phytec/phycore_imx8mp/Kconfig
index 5ede39abc5..bdf9e97bea 100644
--- a/board/phytec/phycore_imx8mp/Kconfig
+++ b/board/phytec/phycore_imx8mp/Kconfig
@@ -52,13 +52,32 @@ config PHYCORE_IMX8MP_RAM_SIZE_8GB
 
 endchoice
 
+config PHYCORE_IMX8MP_RAM_FREQ_FIX
+	bool "Set phyCORE-i.MX8MP RAM frequency fix instead of detecting"
+	default false
+	help
+	  RAM frequency is automatic being detected with the help of
+	  the EEPROM introspection data. Set RAM frequency to a fix value
+	  instead.
+
+choice
+	prompt "phyCORE-i.MX8MP RAM frequency"
+	depends on PHYCORE_IMX8MP_RAM_FREQ_FIX
+	default PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+
 config PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS
 	bool "Use 2GHz RAM timings"
-	depends on PHYCORE_IMX8MP_RAM_SIZE_FIX
-	default false
 	help
 	  Use fix 2GHz RAM timings for phyCORE-i.MX8MP instead of
 	  1.5GHz timings.
 
+config PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS
+	depends on !PHYCORE_IMX8MP_RAM_SIZE_8GB
+	bool "Use 1.5GHz RAM timings"
+	help
+	  Use fix 1.5GHz RAM timings for phyCORE-i.MX8MP instead of
+	  2GHz timings.
+endchoice
+
 source "board/phytec/common/Kconfig"
 endif
diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c
index 7fdb96f1c1..0610d8bbd0 100644
--- a/board/phytec/phycore_imx8mp/spl.c
+++ b/board/phytec/phycore_imx8mp/spl.c
@@ -65,11 +65,21 @@ void spl_dram_init(void)
 			size = PHYTEC_IMX8MP_DDR_4GB;
 		else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_SIZE_8GB))
 			size = PHYTEC_IMX8MP_DDR_8GB;
+	} else {
+		size = phytec_get_imx8m_ddr_size(NULL);
+	}
+
+	if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_RAM_FREQ_FIX)) {
 		if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_2GHZ_RAM_TIMINGS)) {
 			if (size == PHYTEC_IMX8MP_DDR_4GB)
 				size = PHYTEC_IMX8MP_DDR_4GB_2GHZ;
 			else
 				use_2ghz_timings = true;
+		} else if (IS_ENABLED(CONFIG_PHYCORE_IMX8MP_USE_1_5GHZ_RAM_TIMINGS)) {
+			if (size == PHYTEC_IMX8MP_DDR_4GB_2GHZ)
+				size = PHYTEC_IMX8MP_DDR_4GB;
+			else
+				use_2ghz_timings = false;
 		}
 	} else {
 		u8 rev = phytec_get_rev(NULL);
@@ -78,8 +88,6 @@ void spl_dram_init(void)
 		if (rev != PHYTEC_EEPROM_INVAL &&
 		    (rev >= 3 || (somtype == SOM_TYPE_PCL && rev >= 1)))
 			use_2ghz_timings = true;
-
-		size = phytec_get_imx8m_ddr_size(NULL);
 	}
 
 	switch (size) {