From: Peng Fan <peng.fan@nxp.com>
Date: Wed, 6 Apr 2022 06:30:27 +0000 (+0800)
Subject: imx: imx8ulp: enable wdog_ad interrupt in CMC1
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=8c453e9d3d1e5a29cf6ba15234435c043d289621;p=u-boot.git

imx: imx8ulp: enable wdog_ad interrupt in CMC1

Enable wdog_ad interrupt being triggered by CMC1 to CM33 to let CM33
know A35 reset and reinitialize rpmsg.
Clear wdog_ad and AD_PERIPH reset interrupt after A35 up, otherwise
M33 will always receive interrupt.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c
index eb540e3881..569558c7d8 100644
--- a/arch/arm/mach-imx/imx8ulp/soc.c
+++ b/arch/arm/mach-imx/imx8ulp/soc.c
@@ -571,6 +571,19 @@ int arch_cpu_init(void)
 		int ret;
 		bool rdc_en = true; /* Default assume DBD_EN is set */
 
+		/* Enable System Reset Interrupt using WDOG_AD */
+		setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
+		/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
+		setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4));
+
+		if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) {
+			/* Clear System Reset Interrupt Flag Register of WDOG_AD */
+			setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13));
+			/* Reset WDOG to clear reset request */
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true);
+			pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false);
+		}
+
 		/* Disable wdog */
 		init_wdog();