From: Michal Simek <michal.simek@xilinx.com>
Date: Tue, 21 Jan 2014 06:29:47 +0000 (+0100)
Subject: serial: uartlite: Reset RX/TX in init
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=8c3bd6b596300d0ade265329f44832e89ef54a22;p=u-boot.git

serial: uartlite: Reset RX/TX in init

Just to be sure that there is no pending data.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index e6139943ba..988438e754 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -18,10 +18,14 @@
 #define SR_RX_FIFO_VALID_DATA	0x01 /* data in receive FIFO */
 #define SR_RX_FIFO_FULL		0x02 /* receive FIFO full */
 
+#define ULITE_CONTROL_RST_TX	0x01
+#define ULITE_CONTROL_RST_RX	0x02
+
 struct uartlite {
 	unsigned int rx_fifo;
 	unsigned int tx_fifo;
 	unsigned int status;
+	unsigned int control;
 };
 
 static struct uartlite *userial_ports[4] = {
@@ -75,8 +79,16 @@ static int uartlite_serial_tstc(const int port)
 
 static int uartlite_serial_init(const int port)
 {
-	if (userial_ports[port])
+	struct uartlite *regs = userial_ports[port];
+
+	if (regs) {
+		out_be32(&regs->control, 0);
+		out_be32(&regs->control,
+			 ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+		in_be32(&regs->control);
 		return 0;
+	}
+
 	return -1;
 }