From: Ryder Lee Date: Thu, 22 Aug 2019 10:26:52 +0000 (+0200) Subject: arm: dts: split mtk-reset.h into per-chip header X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=898cc1365c1adedeaf033838ab9e767c4dcdcdcf;p=u-boot.git arm: dts: split mtk-reset.h into per-chip header This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 3a868ea2ee..1135b1e1ae 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi index 8ff19162f0..b0c843bafd 100644 --- a/arch/arm/dts/mt7629.dtsi +++ b/arch/arm/dts/mt7629.dtsi @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include "skeleton.dtsi" / { diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mt7623-reset.h similarity index 88% rename from include/dt-bindings/reset/mtk-reset.h rename to include/dt-bindings/reset/mt7623-reset.h index 78fcdab009..a859a5b26a 100644 --- a/include/dt-bindings/reset/mtk-reset.h +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -6,11 +6,9 @@ #ifndef _DT_BINDINGS_MTK_RESET_H_ #define _DT_BINDINGS_MTK_RESET_H_ -/* ETHSYS */ +/* ETHSYS resets */ #define ETHSYS_PPE_RST 31 -#define ETHSYS_EPHY_RST 24 #define ETHSYS_GMAC_RST 23 -#define ETHSYS_ESW_RST 16 #define ETHSYS_FE_RST 6 #define ETHSYS_MCM_RST 2 #define ETHSYS_SYS_RST 0 diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 0000000000..8f1634f7a6 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe Subsystem resets */ +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */