From: Andre Przywara Date: Mon, 12 Feb 2024 23:13:01 +0000 (+0000) Subject: clk: sunxi: a80: Fix reset description X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=7db2f11eb041043d43fe4dd1879d567d33759ee0;p=u-boot.git clk: sunxi: a80: Fix reset description Clock gates and reset lines share a common structure in the sunxi clock driver descriptions, but use different flags to tell them apart. The description of the Allwinner A80 MMC clock reset lines was erroneously using the "GATE" macro, which made the reset driver ignore that entry, complaining with: sunxi_set_reset: (RST-reset:#0) unhandled Change that to the correct "RESET" macro, to make the reset driver happy. Fixes e0c7ce7e52b7 ("sunxi: clk: A80: add MMC clock support") Signed-off-by: Andre Przywara --- diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c index 6751af8a80..091aaeee98 100644 --- a/drivers/clk/sunxi/clk_a80.c +++ b/drivers/clk/sunxi/clk_a80.c @@ -75,10 +75,10 @@ static const struct ccu_clk_gate a80_mmc_gates[] = { }; static const struct ccu_reset a80_mmc_resets[] = { - [0] = GATE(0x0, BIT(18)), - [1] = GATE(0x4, BIT(18)), - [2] = GATE(0x8, BIT(18)), - [3] = GATE(0xc, BIT(18)), + [0] = RESET(0x0, BIT(18)), + [1] = RESET(0x4, BIT(18)), + [2] = RESET(0x8, BIT(18)), + [3] = RESET(0xc, BIT(18)), }; const struct ccu_desc a80_ccu_desc = {