From: Marek Vasut <marex@denx.de>
Date: Tue, 8 May 2018 18:32:01 +0000 (+0200)
Subject: ARM: socfpga: Disable D cache in SPL
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=7544ad0303013e625c9500a4d87d4e5bfe369ee4;p=u-boot.git

ARM: socfpga: Disable D cache in SPL

The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index c97eacb424..c8e73d47c0 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -77,6 +77,8 @@ void spl_board_init(void)
 
 void board_init_f(ulong dummy)
 {
+	dcache_disable();
+
 	socfpga_init_security_policies();
 	socfpga_sdram_remap_zero();
 
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
index 58e446b60a..0f116fbf2d 100644
--- a/include/configs/socfpga_arria10_socdk.h
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -15,8 +15,6 @@
 /*
  * U-Boot general configurations
  */
-/* Cache options */
-#define CONFIG_SYS_DCACHE_OFF
 
 /* Memory configurations  */
 #define PHYS_SDRAM_1_SIZE		0x40000000