From: Zang Roy-r61911 <tie-fei.zang@freescale.com>
Date: Fri, 15 Dec 2006 06:43:31 +0000 (+0800)
Subject: u-boot: Fix CPU2 errata on MPC8548CDS board
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=7337b237ffc4aaf1b9467024fe472a880d852598;p=u-boot.git

u-boot: Fix CPU2 errata on MPC8548CDS board

This patch apply workaround of CPU2 errata on MPC8548CDS board.

Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
---

diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index 7433ebf25b..0d3fcebfe2 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -51,6 +51,7 @@ int checkboard (void)
 {
 	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
+	volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -89,6 +90,12 @@ int checkboard (void)
 	 */
 	local_bus_init ();
 
+	/*
+	 * Fix CPU2 errata: A core hang possible while executing a
+	 * msync instruction and a snoopable transaction from an I/O
+	 * master tagged to make quick forward progress is present.
+	 */
+	ecm->eebpcr |= (1 << 16);
 
 	/*
 	 * Hack TSEC 3 and 4 IO voltages.