From: Vignesh Raghavendra <vigneshr@ti.com>
Date: Mon, 7 Mar 2022 09:25:51 +0000 (+0530)
Subject: ARM: dts: k3-j721s2: Correct timer frequency
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=7262ff7e564c8b7d81f940af242c20f832ee7511;p=u-boot.git

ARM: dts: k3-j721s2: Correct timer frequency

MCU Timer0 runs at 250MHz, and the clock-frequency defined in DT appears
incorrect.

Without this delays in R5 SPL are 10x off.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---

diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 749bc717f3..a17e61eccf 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -40,7 +40,7 @@
 		compatible = "ti,omap5430-timer";
 		reg = <0x0 0x40400000 0x0 0x80>;
 		ti,timer-alwon;
-		clock-frequency = <25000000>;
+		clock-frequency = <250000000>;
 		u-boot,dm-spl;
 	};