From: Kever Yang Date: Fri, 23 Jun 2017 08:11:05 +0000 (+0800) Subject: rockchip: add sdram_common for common functions X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=6d1970fa8a8d315af2b5c2c6f0ad5e5c24a382b5;p=u-boot.git rockchip: add sdram_common for common functions There are some functions like sdram_size_mb can be re-used for different rockchip SoCs, just put them into common file. Add board_get_usable_ram_top() for ram_top init base on SDRAM_MAX_SIZE. Signed-off-by: Kever Yang Reviewed-by: Philipp Tomsich Added SDRAM_MAX_SIZE definition for RK3036: Signed-off-by: Philipp Tomsich fixup: 3036 fix for sdram_common --- diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h b/arch/arm/include/asm/arch-rockchip/sdram_common.h new file mode 100644 index 0000000000..fec85865ff --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_SDRAM_COMMON_H +#define _ASM_ARCH_SDRAM_COMMON_H +/* + * sys_reg bitfield struct + * [31] row_3_4_ch1 + * [30] row_3_4_ch0 + * [29:28] chinfo + * [27] rank_ch1 + * [26:25] col_ch1 + * [24] bk_ch1 + * [23:22] cs0_row_ch1 + * [21:20] cs1_row_ch1 + * [19:18] bw_ch1 + * [17:16] dbw_ch1; + * [15:13] ddrtype + * [12] channelnum + * [11] rank_ch0 + * [10:9] col_ch0 + * [8] bk_ch0 + * [7:6] cs0_row_ch0 + * [5:4] cs1_row_ch0 + * [3:2] bw_ch0 + * [1:0] dbw_ch0 +*/ +#define SYS_REG_DDRTYPE_SHIFT 13 +#define SYS_REG_DDRTYPE_MASK 7 +#define SYS_REG_NUM_CH_SHIFT 12 +#define SYS_REG_NUM_CH_MASK 1 +#define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) +#define SYS_REG_ROW_3_4_MASK 1 +#define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) +#define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) +#define SYS_REG_RANK_MASK 1 +#define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) +#define SYS_REG_COL_MASK 3 +#define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) +#define SYS_REG_BK_MASK 1 +#define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) +#define SYS_REG_CS0_ROW_MASK 3 +#define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) +#define SYS_REG_CS1_ROW_MASK 3 +#define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) +#define SYS_REG_BW_MASK 3 +#define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) +#define SYS_REG_DBW_MASK 3 + +/* Get sdram size decode from reg */ +size_t rockchip_sdram_size(phys_addr_t reg); + +/* Called by U-Boot board_init_r for Rockchip SoCs */ +int dram_init(void); +#endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 87d201995e..5ac82d06be 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -19,6 +19,9 @@ else obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o +ifdef CONFIG_RAM +obj-y += sdram_common.o +endif endif ifndef CONFIG_ARM64 obj-y += rk_timer.o diff --git a/arch/arm/mach-rockchip/sdram_common.c b/arch/arm/mach-rockchip/sdram_common.c new file mode 100644 index 0000000000..76dbdc8715 --- /dev/null +++ b/arch/arm/mach-rockchip/sdram_common.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2017 Rockchip Electronics Co., Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +size_t rockchip_sdram_size(phys_addr_t reg) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + + u32 sys_reg = readl(reg); + u32 ch_num = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) + & SYS_REG_NUM_CH_MASK); + + debug("%s %x %x\n", __func__, (u32)reg, sys_reg); + for (ch = 0; ch < ch_num; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + debug("rank %d col %d bk %d cs0_row %d bw %d row_3_4 %d\n", + rank, col, bk, cs0_row, bw, row_3_4); + } + + return (size_t)size_mb << 20; +} + +int dram_init(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + ret = ram_get_info(dev, &ram); + if (ret) { + debug("Cannot get DRAM size: %d\n", ret); + return ret; + } + gd->ram_size = ram.size; + debug("SDRAM base=%lx, size=%lx\n", + (unsigned long)ram.base, (unsigned long)ram.size); + + return 0; +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + + return (gd->ram_top > top) ? top : gd->ram_top; +} diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 836c5e3fed..1f6b5a1669 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (512UL << 20UL) +#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) #define CONFIG_SPI_FLASH #define CONFIG_SPI diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h index a1e0eb7c8d..7f57dd3141 100644 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@ -64,6 +64,7 @@ #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0x80000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index ecf2675255..7d6ef41368 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -48,6 +48,7 @@ #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 #define SDRAM_BANK_SIZE (2UL << 30) +#define SDRAM_MAX_SIZE 0xfe000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 5a06244594..7f9f0c5534 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -9,7 +9,6 @@ #include "rockchip-common.h" -#define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (32 << 20) @@ -37,6 +36,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 #define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SPI_FLASH #define CONFIG_SPI diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8ebf2324c5..b0c858c693 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -12,6 +12,8 @@ #include #include +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_MAXARGS 16 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index 44dad570d3..54ea97b164 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -51,6 +51,7 @@ /* FAT sd card locations. */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xf8000000 #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SF_DEFAULT_SPEED 20000000