From: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Date: Mon, 22 Mar 2021 18:58:38 +0000 (-0700)
Subject: arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=65a572b1d0faeffd6fa467c1115c13a8831316e3;p=u-boot.git

arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node

The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed.  Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index 135c83f502..e5d75e5523 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx Versal a2197 RevA System Controller
  *
- * (C) Copyright 2019 - 2020, Xilinx, Inc.
+ * (C) Copyright 2019 - 2021, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -505,6 +505,7 @@
 				factory-fout = <200000000>;
 				clock-frequency = <200000000>;
 				clock-output-names = "si570_ddrdimm1_clk";
+				silabs,skip-recall;
 			};
 		};
 		i2c@4 { /* LPDDR4_SI570_CLK2 */