From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 3 Jun 2015 01:20:06 +0000 (+0800)
Subject: x86: qemu: Implement PIRQ routing
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=5c564226fc8948e435edea8eb8c5c4afbc5edef1;p=u-boot.git

x86: qemu: Implement PIRQ routing

Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c4cac045b2..0e9f15fef6 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -89,3 +89,8 @@ int misc_init_r(void)
 {
 	return 0;
 }
+
+int arch_misc_init(void)
+{
+	return 0;
+}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 0f984768e9..930d2b6c9d 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/irq.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 
@@ -35,3 +36,10 @@ void reset_cpu(ulong addr)
 	/* cold reset */
 	x86_full_reset();
 }
+
+int arch_misc_init(void)
+{
+	pirq_init();
+
+	return 0;
+}
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index 4cf843b813..557428a459 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 
@@ -29,6 +31,20 @@
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		irq-router@1,0 {
+			reg = <0x00000800 0 0 0 0>;
+			compatible = "intel,irq-router";
+			intel,pirq-config = "pci";
+			intel,pirq-link = <0x60 4>;
+			intel,pirq-mask = <0x0e40>;
+			intel,pirq-routing = <
+				/* PIIX UHCI */
+				PCI_BDF(0, 1, 2) INTD PIRQD
+				/* e1000 NIC */
+				PCI_BDF(0, 3, 0) INTA PIRQC
+			>;
+		};
 	};
 
 };
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 02a483cd37..c259f2a3d2 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -6,6 +6,18 @@
 
 /dts-v1/;
 
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+/* ICH9 IRQ router has discrete PIRQ control registers */
+#undef PIRQE
+#undef PIRQF
+#undef PIRQG
+#undef PIRQH
+#define PIRQE	8
+#define PIRQF	9
+#define PIRQG	10
+#define PIRQH	11
+
 /include/ "skeleton.dtsi"
 /include/ "serial.dtsi"
 
@@ -30,6 +42,26 @@
 		ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
 			0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
 			0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		irq-router@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "intel,irq-router";
+			intel,pirq-config = "pci";
+			intel,pirq-link = <0x60 8>;
+			intel,pirq-mask = <0x0e40>;
+			intel,pirq-routing = <
+				/* e1000 NIC */
+				PCI_BDF(0, 2, 0) INTA PIRQG
+				/* ICH9 UHCI */
+				PCI_BDF(0, 29, 0) INTA PIRQA
+				PCI_BDF(0, 29, 1) INTB PIRQB
+				PCI_BDF(0, 29, 2) INTC PIRQC
+				/* ICH9 EHCI */
+				PCI_BDF(0, 29, 7) INTD PIRQD
+				/* ICH9 SATA */
+				PCI_BDF(0, 31, 2) INTA PIRQA
+			>;
+		};
 	};
 
 };
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 0959a98283..901cbd72a9 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -2,6 +2,7 @@ CONFIG_X86=y
 CONFIG_VENDOR_EMULATION=y
 CONFIG_DEFAULT_DEVICE_TREE="qemu-x86_i440fx"
 CONFIG_TARGET_QEMU_X86=y
+CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_CMD_NET=y
 CONFIG_OF_CONTROL=y
 CONFIG_VIDEO_VESA=y
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h
index d01936b47b..78c296f5ad 100644
--- a/include/configs/qemu-x86.h
+++ b/include/configs/qemu-x86.h
@@ -14,6 +14,7 @@
 #include <configs/x86-common.h>
 
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_ARCH_MISC_INIT
 
 #define CONFIG_X86_SERIAL