From: Stefan Roese <sr@denx.de>
Date: Mon, 7 Nov 2005 12:43:06 +0000 (+0100)
Subject: Fix MPC85xx PCI support (pci_register_hose() before pci config access)
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=527b5a511c804074eebfc08c9ae7860b6717da85;p=u-boot.git

Fix MPC85xx PCI support (pci_register_hose() before pci config access)
Patch by Stefan Roese, 07 Nov 2005
---

diff --git a/CHANGELOG b/CHANGELOG
index df3003e4ca..5c6d68fff0 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes for U-Boot 1.1.4:
 ======================================================================
 
+* Fix MPC85xx PCI support (pci_register_hose() before pci config access)
+  Patch by Stefan Roese, 07 Nov 2005
+
 * Correct PPC Timebase register definitions (SPRN_TBRL...)
   Patch by Stefan Roese, 07 Nov 2005
 
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 069fe4e69a..a94493e080 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -61,16 +61,6 @@ pci_mpc85xx_init(struct pci_controller *hose)
 			   (CFG_IMMR+0x8000),
 			   (CFG_IMMR+0x8004));
 
-	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
-	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
-
 	pcix->potar1   = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
 	pcix->potear1  = 0x00000000;
 	pcix->powbar1  = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
@@ -93,6 +83,16 @@ pci_mpc85xx_init(struct pci_controller *hose)
 	 */
 	pci_register_hose(hose);
 
+	pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
+	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
+
+	/*
+	 * Clear non-reserved bits in status register.
+	 */
+	pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
+	pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
+
 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
 	/*
 	 * This is a SW workaround for an apparent HW problem