From: Michael Walle <michael@walle.cc>
Date: Wed, 13 Oct 2021 16:14:08 +0000 (+0200)
Subject: arm: dts: ls1028a: move the UART controller nodes into /soc
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=44800f2b4f7fb49520b9142037d6eacce18a32ce;p=u-boot.git

arm: dts: ls1028a: move the UART controller nodes into /soc

While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
---

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index ecafa67d08..07aeb380ef 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -43,22 +43,6 @@
 					  IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-	serial0: serial@21c0500 {
-		device_type = "serial";
-		compatible = "fsl,ns16550", "ns16550a";
-		reg = <0x0 0x21c0500 0x0 0x100>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-	};
-
-	serial1: serial@21c0600 {
-		device_type = "serial";
-		compatible = "fsl,ns16550", "ns16550a";
-		reg = <0x0 0x21c0600 0x0 0x100>;
-		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-	};
-
 	pcie1: pcie@3400000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03400000 0x0 0x80000
@@ -484,5 +468,21 @@
 			bus-width = <4>;
 			status = "disabled";
 		};
+
+		serial0: serial@21c0500 {
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x0 0x21c0500 0x0 0x100>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		serial1: serial@21c0600 {
+			device_type = "serial";
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x0 0x21c0600 0x0 0x100>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
 	};
 };