From: Stefan Roese <sr@denx.de>
Date: Tue, 25 Aug 2015 12:09:12 +0000 (+0200)
Subject: arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=42cc034f19d30a3e0f1a63788347e039315806a0;p=u-boot.git

arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPL

When running on the AXP I sometimes noticed a strange behavior. As some
characters are not echoed on the U-Boot prompt. Not disabling the
lowlevel_init code, especially calling cpu_init_cp15() in the main
U-Boot seems to solve this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index efd4d04ea8..895ad929b1 100644
--- a/arch/arm/mach-mvebu/cpu.c
+++ b/arch/arm/mach-mvebu/cpu.c
@@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
 	  CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
 };
 
+void lowlevel_init(void)
+{
+	/*
+	 * Dummy implementation, we only need LOWLEVEL_INIT
+	 * on Armada to configure CP15 in start.S / cpu_init_cp15()
+	 */
+}
+
 void reset_cpu(unsigned long ignored)
 {
 	struct mvebu_system_registers *reg =
@@ -214,7 +222,10 @@ static void setup_usb_phys(void)
 
 int arch_cpu_init(void)
 {
-#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
+#if !defined(CONFIG_SPL_BUILD)
+	struct pl310_regs *const pl310 =
+		(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
+
 	/*
 	 * Only with disabled MMU its possible to switch the base
 	 * register address on Armada 38x. Without this the SDRAM
@@ -234,18 +245,14 @@ int arch_cpu_init(void)
 	 * configured the internal register base to the value used
 	 * in the macros / defines in the U-Boot header (soc.h).
 	 */
-	if (mvebu_soc_family() == MVEBU_SOC_A38X) {
-		struct pl310_regs *const pl310 =
-			(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 
-		/*
-		 * To fully release / unlock this area from cache, we need
-		 * to flush all caches and disable the L2 cache.
-		 */
-		icache_disable();
-		dcache_disable();
-		clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-	}
+	/*
+	 * To fully release / unlock this area from cache, we need
+	 * to flush all caches and disable the L2 cache.
+	 */
+	icache_disable();
+	dcache_disable();
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 #endif
 
 	/*
diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h
index 1dd4182136..15f7bdfac5 100644
--- a/include/configs/db-88f6820-gp.h
+++ b/include/configs/db-88f6820-gp.h
@@ -16,7 +16,9 @@
 
 #define CONFIG_SYS_L2_PL310
 
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index f612e72d88..5b39762303 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -13,7 +13,9 @@
 #define CONFIG_ARMADA_XP		/* SOC Family Name */
 #define CONFIG_DB_784MP_GP		/* Board target name for DDR training */
 
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 3530a26213..3bed9c7ca4 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -11,7 +11,9 @@
  * High Level Configuration Options (easy to change)
  */
 #define CONFIG_ARMADA_XP		/* SOC Family Name */
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+#endif
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO_LATE