From: Tom Rini <trini@konsulko.com>
Date: Mon, 4 Mar 2024 16:50:26 +0000 (-0500)
Subject: Merge patch series "board: beagle: Enable 32k and debounce configuration and fixups"
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=3ba443abdb4019d7f5adc179ef7016be7778f73d;p=u-boot.git

Merge patch series "board: beagle: Enable 32k and debounce configuration and fixups"

Nishanth Menon <nm@ti.com> says:

Hi,

Rev 2 of the series.

This is a follow up from [1] - Without the 32k crystal configuration,
wlan doesn't work. Debounce is needed for HDMI Hot plug detect(hpd)
gpio interrupt not storming.

At least the 32k configuration has been done for toradex and phytec
boards, follow similar model of programming.

Series is now based off master branch.

Bootlog: https://gist.github.com/nmenon/75df38bee907785d1d78d1ec4abd7304

Changes from V2:
- Removed depedency on [2] - depending on which way
  the merge sequence goes, one of the series will need a rebase.
- Added a patch for a bug that Jan noticed
- Fixup for the fat finger missing 0x in 0x4080 :(

[1] https://lore.kernel.org/u-boot/20230725185253.2123433-4-nm@ti.com/
[2] https://lore.kernel.org/u-boot/20240212194726.1093771-1-nm@ti.com/
---

3ba443abdb4019d7f5adc179ef7016be7778f73d
diff --cc board/beagle/beagleplay/beagleplay.c
index 20819ecf45,fe1c4f9203..af36439e2e
--- a/board/beagle/beagleplay/beagleplay.c
+++ b/board/beagle/beagleplay/beagleplay.c
@@@ -28,16 -30,61 +30,75 @@@ int dram_init_banksize(void
  	return fdtdec_setup_memory_banksize();
  }
  
 +#ifdef CONFIG_BOARD_LATE_INIT
 +int board_late_init(void)
 +{
 +	char fdtfile[50];
 +
 +	snprintf(fdtfile, sizeof(fdtfile), "%s/%s.dtb",
 +		 CONFIG_TI_FDT_FOLDER_PATH, CONFIG_DEFAULT_DEVICE_TREE);
 +
 +	env_set("fdtfile", fdtfile);
 +
 +	return 0;
 +}
 +#endif
++
+ #ifdef CONFIG_SPL_BOARD_INIT
+ 
+ /*
+  * Enable the 32k Crystal: needed for accurate 32k clock
+  * and external clock sources such as wlan 32k input clock
+  * supplied from the SoC to the wlan chip.
+  *
+  * The trim setup can be very highly board type specific choice of the crystal
+  * So this is done in the board file, though, in this case, no specific trim
+  * is necessary.
+  */
+ static void crystal_32k_enable(void)
+ {
+ 	/* Only mess with 32k at the start of boot from R5 */
+ 	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ 		/*
+ 		 * We have external 32k crystal, so lets enable it (0x0)
+ 		 * and disable bypass (0x0)
+ 		 */
+ 		writel(0x0, MCU_CTRL_LFXOSC_CTRL);
+ 
+ 		/* Add any crystal specific TRIM needed here.. */
+ 
+ 		/* Make sure to mux the SoC 32k from the crystal */
+ 		writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL,
+ 		       MCU_CTRL_DEVICE_CLKOUT_32K_CTRL);
+ 	}
+ }
+ 
+ static void debounce_configure(void)
+ {
+ 	/* Configure debounce one time from R5 */
+ 	if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ 		/*
+ 		 * Setup debounce time registers.
+ 		 * arbitrary values. Times are approx
+ 		 */
+ 		/* 1.9ms debounce @ 32k */
+ 		writel(0x1, CTRLMMR_DBOUNCE_CFG(1));
+ 		/* 5ms debounce @ 32k */
+ 		writel(0x5, CTRLMMR_DBOUNCE_CFG(2));
+ 		/* 20ms debounce @ 32k */
+ 		writel(0x14, CTRLMMR_DBOUNCE_CFG(3));
+ 		/* 46ms debounce @ 32k */
+ 		writel(0x18, CTRLMMR_DBOUNCE_CFG(4));
+ 		/* 100ms debounce @ 32k */
+ 		writel(0x1c, CTRLMMR_DBOUNCE_CFG(5));
+ 		/* 156ms debounce @ 32k */
+ 		writel(0x1f, CTRLMMR_DBOUNCE_CFG(6));
+ 	}
+ }
+ 
+ void spl_board_init(void)
+ {
+ 	crystal_32k_enable();
+ 	debounce_configure();
+ }
+ #endif