From: York Sun Date: Mon, 6 Mar 2017 17:02:28 +0000 (-0800) Subject: armv8: layerscape: Rewrite memory reservation X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=36cc0de0b919c0e185739142742e0a76a7c5c30a;p=u-boot.git armv8: layerscape: Rewrite memory reservation For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved at the end of DDR. DDR is spit into two or three banks. This patch reverts commit aabd7ddb and simplifies the calculation of reserved memory, and moves the code into common SoC file. Secure memory is carved out first. DDR bank size is reduced. Reserved memory is then allocated on the top of available memory. U-Boot still has access to reserved memory as data transferring is needed. Device tree is fixed with reduced memory size to hide the reserved memory from OS. The same region is reserved for efi_loader. Signed-off-by: York Sun --- diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225181..d0be335b2f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -524,15 +524,201 @@ phys_size_t board_reserve_ram_top(phys_size_t ram_size) { phys_size_t ram_top = ram_size; -#ifdef CONFIG_SYS_MEM_TOP_HIDE -#error CONFIG_SYS_MEM_TOP_HIDE not to be used together with this function -#endif - -/* Carve the MC private DRAM block from the end of DRAM */ #ifdef CONFIG_FSL_MC_ENET + /* The start address of MC reserved memory needs to be aligned. */ ram_top -= mc_get_dram_block_size(); ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1); #endif - return ram_top; + return ram_size - ram_top; +} + +phys_size_t get_effective_memsize(void) +{ + phys_size_t ea_size, rem = 0; + + /* + * For ARMv8 SoCs, DDR memory is split into two or three regions. The + * first region is 2GB space at 0x8000_0000. If the memory extends to + * the second region (or the third region if applicable), the secure + * memory and Management Complex (MC) memory should be put into the + * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED + * is set to the size of first region so U-Boot doesn't relocate itself + * into higher address. Should DDR be configured to skip the first + * region, this function needs to be adjusted. + */ + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + ea_size = CONFIG_MAX_MEM_MAPPED; + rem = gd->ram_size - ea_size; + } else { + ea_size = gd->ram_size; + } + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* Check if we have enough space for secure memory */ + if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) { + rem -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else { + if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) { + ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + rem = 0; /* Presume MC requires more memory */ + } else { + printf("Error: No enough space for secure memory.\n"); + } + } +#endif + /* Check if we have enough memory for MC */ + if (rem < board_reserve_ram_top(rem)) { + /* Not enough memory in high region to reserve */ + if (ea_size > board_reserve_ram_top(rem)) + ea_size -= board_reserve_ram_top(rem); + else + printf("Error: No enough space for reserved memory.\n"); + } + + return ea_size; +} + +void dram_init_banksize(void) +{ +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY + phys_size_t dp_ddr_size; +#endif + + /* + * gd->ram_size has the total size of DDR memory, less reserved secure + * memory. The DDR extends from low region to high region(s) presuming + * no hole is created with DDR configuration. gd->arch.secure_ram tracks + * the location of secure memory. gd->arch.resv_ram tracks the location + * of reserved memory for Management Complex (MC). + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { + gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; + gd->bd->bi_dram[1].size = gd->ram_size - + CONFIG_SYS_DDR_BLOCK1_SIZE; +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE; + gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size - + CONFIG_SYS_DDR_BLOCK2_SIZE; + gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE; + } +#endif + } else { + gd->bd->bi_dram[0].size = gd->ram_size; + } +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else +#endif + { + if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[1].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } else if (gd->bd->bi_dram[0].size > + CONFIG_SYS_MEM_RESERVE_SECURE) { + gd->bd->bi_dram[0].size -= + CONFIG_SYS_MEM_RESERVE_SECURE; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; + } + } +#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */ + +#ifdef CONFIG_FSL_MC_ENET + /* Assign memory for MC */ +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE + if (gd->bd->bi_dram[2].size >= + board_reserve_ram_top(gd->bd->bi_dram[2].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[2].start + + gd->bd->bi_dram[2].size - + board_reserve_ram_top(gd->bd->bi_dram[2].size); + } else +#endif + { + if (gd->bd->bi_dram[1].size >= + board_reserve_ram_top(gd->bd->bi_dram[1].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[1].start + + gd->bd->bi_dram[1].size - + board_reserve_ram_top(gd->bd->bi_dram[1].size); + } else if (gd->bd->bi_dram[0].size > + board_reserve_ram_top(gd->bd->bi_dram[0].size)) { + gd->arch.resv_ram = gd->bd->bi_dram[0].start + + gd->bd->bi_dram[0].size - + board_reserve_ram_top(gd->bd->bi_dram[0].size); + } + } +#endif /* CONFIG_FSL_MC_ENET */ + +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (soc_has_dp_ddr()) { + /* initialize DP-DDR here */ + puts("DP-DDR: "); + /* + * DDR controller use 0 as the base address for binding. + * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. + */ + dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, + CONFIG_DP_DDR_CTRL, + CONFIG_DP_DDR_NUM_CTRLS, + CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, + NULL, NULL, NULL); + if (dp_ddr_size) { + gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; + gd->bd->bi_dram[2].size = dp_ddr_size; + } else { + puts("Not detected"); + } + } +#endif +} + +#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) +void efi_add_known_memory(void) +{ + int i; + phys_addr_t ram_start, start; + phys_size_t ram_size; + u64 pages; + + /* Add RAM */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { +#ifdef CONFIG_SYS_DP_DDR_BASE_PHY +#ifdef CONFIG_SYS_DDR_BLOCK3_BASE +#error "This SoC shouldn't have DP DDR" +#endif + if (i == 2) + continue; /* skip DP-DDR */ +#endif + ram_start = gd->bd->bi_dram[i].start; + ram_size = gd->bd->bi_dram[i].size; +#ifdef CONFIG_RESV_RAM + if (gd->arch.resv_ram >= ram_start && + gd->arch.resv_ram < ram_start + ram_size) + ram_size = gd->arch.resv_ram - ram_start; +#endif + start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK; + pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT; + + efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY, + false); + } } +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 586ce17215..b5b08aae23 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -33,8 +33,8 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ /* DDR */ -#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define CONFIG_SYS_FSL_CCSR_GUR_LE #define CONFIG_SYS_FSL_CCSR_SCFG_LE diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 789cae225b..1f3adc1e88 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -91,32 +91,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 4281790426..fbda504c04 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -166,32 +166,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index e3a8a7631b..2a85a1f8f7 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -165,32 +165,3 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } - -void dram_init_banksize(void) -{ - /* - * gd->secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 7882a9a9a1..c740062887 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -127,32 +127,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 849f1d1b66..f90b85df1a 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -188,32 +188,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046aqds/ddr.c b/board/freescale/ls1046aqds/ddr.c index 4ea8b236bf..dc4d689adc 100644 --- a/board/freescale/ls1046aqds/ddr.c +++ b/board/freescale/ls1046aqds/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls1046ardb/ddr.c b/board/freescale/ls1046ardb/ddr.c index dd3b5d0e6b..efe2ba6eb1 100644 --- a/board/freescale/ls1046ardb/ddr.c +++ b/board/freescale/ls1046ardb/ddr.c @@ -112,32 +112,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } -} diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index e6130ec709..5ed9e1461b 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080a/ls2080a.c b/board/freescale/ls2080a/ls2080a.c index 4f9b9c8a77..21ea70bd4d 100644 --- a/board/freescale/ls2080a/ls2080a.c +++ b/board/freescale/ls2080a/ls2080a.c @@ -123,6 +123,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); #ifdef CONFIG_FSL_MC_ENET diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index 9c6f477c7f..0408c0fc25 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -169,58 +169,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 73a61fd75a..ec53992bcc 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -313,6 +313,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index 959dfeb02b..2851d5b443 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -172,58 +172,3 @@ phys_size_t initdram(int board_type) return dram_size; } - -void dram_init_banksize(void) -{ -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - phys_size_t dp_ddr_size; -#endif - - /* - * gd->arch.secure_ram tracks the location of secure memory. - * It was set as if the memory starts from 0. - * The address needs to add the offset of its bank. - */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) { - gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; - gd->bd->bi_dram[1].size = gd->ram_size - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[1].start + - gd->arch.secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } else { - gd->bd->bi_dram[0].size = gd->ram_size; -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->arch.secure_ram = gd->bd->bi_dram[0].start + - gd->arch.secure_ram; - gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; -#endif - } - -#ifdef CONFIG_SYS_DP_DDR_BASE_PHY - if (soc_has_dp_ddr()) { - /* initialize DP-DDR here */ - puts("DP-DDR: "); - /* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ - dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY, - CONFIG_DP_DDR_CTRL, - CONFIG_DP_DDR_NUM_CTRLS, - CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR, - NULL, NULL, NULL); - if (dp_ddr_size) { - gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE; - gd->bd->bi_dram[2].size = dp_ddr_size; - } else { - puts("Not detected"); - } - } -#endif -} diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 02954ef6d7..7a4c6a3a5c 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -202,14 +202,6 @@ int misc_init_r(void) if (adjust_vdd(0)) printf("Warning: Adjusting core voltage failed.\n"); -#if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD) - if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) { - efi_add_memory_map(gd->bd->bi_dram[2].start, - gd->bd->bi_dram[2].size >> EFI_PAGE_SHIFT, - EFI_RESERVED_MEMORY_TYPE, false); - } -#endif - return 0; } @@ -286,6 +278,16 @@ int ft_board_setup(void *blob, bd_t *bd) base[1] = gd->bd->bi_dram[1].start; size[1] = gd->bd->bi_dram[1].size; +#ifdef CONFIG_RESV_RAM + /* reduce size if reserved memory is within this bank */ + if (gd->arch.resv_ram >= base[0] && + gd->arch.resv_ram < base[0] + size[0]) + size[0] = gd->arch.resv_ram - base[0]; + else if (gd->arch.resv_ram >= base[1] && + gd->arch.resv_ram < base[1] + size[1]) + size[1] = gd->arch.resv_ram - base[1]; +#endif + fdt_fixup_memory_banks(blob, base, size, 2); fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/common/board_f.c b/common/board_f.c index ae6cd8528c..7d1ede0404 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -325,15 +325,6 @@ __weak ulong board_get_usable_ram_top(ulong total_size) return gd->ram_top; } -__weak phys_size_t board_reserve_ram_top(phys_size_t ram_size) -{ -#ifdef CONFIG_SYS_MEM_TOP_HIDE - return ram_size - CONFIG_SYS_MEM_TOP_HIDE; -#else - return ram_size; -#endif -} - static int setup_dest_addr(void) { debug("Monitor len: %08lX\n", gd->mon_len); @@ -341,26 +332,19 @@ static int setup_dest_addr(void) * Ram is setup, size stored in gd !! */ debug("Ram size: %08lX\n", (ulong)gd->ram_size); -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE - /* Reserve memory for secure MMU tables, and/or security monitor */ - gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE; - /* - * Record secure memory location. Need recalcuate if memory splits - * into banks, or the ram base is not zero. - */ - gd->arch.secure_ram = gd->ram_size; -#endif +#if defined(CONFIG_SYS_MEM_TOP_HIDE) /* * Subtract specified amount of memory to hide so that it won't * get "touched" at all by U-Boot. By fixing up gd->ram_size * the Linux kernel should now get passed the now "corrected" - * memory size and won't touch it either. This has been used - * by arch/powerpc exclusively. Now ARMv8 takes advantage of - * thie mechanism. If memory is split into banks, addresses - * need to be calculated. + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. */ - gd->ram_size = board_reserve_ram_top(gd->ram_size); - + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif #ifdef CONFIG_SYS_SDRAM_BASE gd->ram_top = CONFIG_SYS_SDRAM_BASE; #endif diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 079082a26f..231a6d5ffa 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -714,21 +714,7 @@ int get_dpl_apply_status(void) */ u64 mc_get_dram_addr(void) { - u64 mc_ram_addr; - - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } - - return mc_ram_addr; + return gd->arch.resv_ram; } /**