From: Tom Rini Date: Mon, 11 Jul 2022 14:18:13 +0000 (-0400) Subject: Merge branch 'next' X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=36b661dc919da318c163a45f4a220d2e3d9db608;p=u-boot.git Merge branch 'next' --- 36b661dc919da318c163a45f4a220d2e3d9db608 diff --cc configs/imx8mn_bsh_smm_s2_defconfig index f8c75a2b23,5013dc5895..79995591f2 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@@ -26,14 -26,22 +26,24 @@@ CONFIG_OF_SYSTEM_SETUP= CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_LATE_INIT=y + CONFIG_SPL_MAX_SIZE=0x25000 + CONFIG_SPL_HAS_BSS_LINKER_SECTION=y + CONFIG_SPL_BSS_START_ADDR=0x950000 + CONFIG_SPL_BSS_MAX_SIZE=0x2000 CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SPL_STACK=0x980000 + CONFIG_SYS_SPL_MALLOC=y + CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y + CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x42200000 + CONFIG_SYS_SPL_MALLOC_SIZE=0x80000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 +CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_POWER=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_PROMPT="> " diff --cc configs/kontron-sl-mx8mm_defconfig index f453ace625,17658d5334..344f627bf5 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@@ -100,10 -111,9 +112,10 @@@ CONFIG_DM_PMIC= CONFIG_DM_PMIC_PCA9450=y CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y - CONFIG_CONS_INDEX=2 + CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --cc configs/pinebook-pro-rk3399_defconfig index aaa52c6ea7,af473f9136..602bcb78cb --- a/configs/pinebook-pro-rk3399_defconfig +++ b/configs/pinebook-pro-rk3399_defconfig @@@ -20,9 -21,17 +22,16 @@@ CONFIG_USE_PREBOOT= CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-pinebook-pro.dtb" CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_MISC_INIT_R=y + CONFIG_SPL_MAX_SIZE=0x2e000 + CONFIG_SPL_PAD_TO=0x7f8000 + CONFIG_SPL_HAS_BSS_LINKER_SECTION=y + CONFIG_SPL_BSS_START_ADDR=0x400000 + CONFIG_SPL_BSS_MAX_SIZE=0x2000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set + # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set + CONFIG_SPL_STACK=0x400000 CONFIG_SPL_STACK_R=y CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 -CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_TPL=y CONFIG_CMD_BOOTZ=y diff --cc configs/socfpga_chameleonv3_defconfig index 12f3950d44,0000000000..e78d3b51de mode 100644,000000..100644 --- a/configs/socfpga_chameleonv3_defconfig +++ b/configs/socfpga_chameleonv3_defconfig @@@ -1,28 -1,0 +1,34 @@@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2" +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y +CONFIG_SPL_FS_FAT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_SPL_FIT=y +# CONFIG_USE_SPL_FIT_GENERATOR is not set +CONFIG_MISC_INIT_R=y ++CONFIG_SPL_NO_BSS_LIMIT=y ++CONFIG_SYS_SPL_MALLOC=y ++CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y ++CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0xffe2b000 ++CONFIG_SYS_SPL_MALLOC_SIZE=0x15000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_FPGA=y ++CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_ATSHA204A=y +CONFIG_FS_LOADER=y +CONFIG_SPL_FS_LOADER=y +CONFIG_MMC_DW=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_DESIGNWARE_APB_TIMER=y diff --cc include/configs/imx8mn_bsh_smm_s2.h index d09c2ab016,84c19824bd..c6b2962814 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@@ -14,11 -14,8 +14,9 @@@ #include #define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs " \ + "nandargs=setenv bootargs console=${console} " \ "${optargs} " \ + "mtdparts=${mtdparts} " \ "root=${nandroot} " \ "rootfstype=${nandrootfstype}\0" \ "nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \ diff --cc include/configs/rk3036_common.h index f4f6bcab5e,ac57721f02..6616396777 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@@ -8,13 -8,11 +8,8 @@@ #include #include "rockchip-common.h" - #define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_HZ_CLOCK 24000000 - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - #define CONFIG_SPL_STACK 0x10081fff -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" -- #define CONFIG_SYS_SDRAM_BASE 0x60000000 #define SDRAM_BANK_SIZE (512UL << 20UL) #define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) diff --cc include/configs/rk3188_common.h index 5c4dfa61e0,56fba3ff25..6fe1b2d9a2 --- a/include/configs/rk3188_common.h +++ b/include/configs/rk3188_common.h @@@ -9,13 -9,8 +9,6 @@@ #include #include "rockchip-common.h" - #define CONFIG_SYS_CBSIZE 1024 - - #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM - /* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ - #endif - #define CONFIG_SYS_INIT_SP_ADDR 0x60100000 - -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" #define CONFIG_IRAM_BASE 0x10080000 /* spl size 32kb sram - 2kb bootrom */ diff --cc include/configs/rk322x_common.h index f66a7d23be,ec9e9ca1e3..4fb86b69a8 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@@ -8,14 -8,10 +8,8 @@@ #include #include "rockchip-common.h" - #define CONFIG_SYS_CBSIZE 1024 - #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - #define CONFIG_SYS_HZ_CLOCK 24000000 - #define CONFIG_SYS_INIT_SP_ADDR 0x61100000 - #define CONFIG_SPL_MAX_SIZE 0x100000 - -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK32" #define CONFIG_IRAM_BASE 0x10080000 #define CONFIG_SYS_SDRAM_BASE 0x60000000 diff --cc include/configs/socfpga_chameleonv3.h index 891b762946,0000000000..75d2081fac mode 100644,000000..100644 --- a/include/configs/socfpga_chameleonv3.h +++ b/include/configs/socfpga_chameleonv3.h @@@ -1,44 -1,0 +1,39 @@@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022 Google LLC + */ +#ifndef __SOCFGPA_CHAMELEONV3_H__ +#define __SOCFGPA_CHAMELEONV3_H__ + +#include + - #define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) - +/* + * U-Boot general configurations + */ + +/* Memory configurations */ +#define PHYS_SDRAM_1_SIZE 0x40000000 + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \ + "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \ + "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \ + "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0" + +/* + * L4 OSC1 Timer 0 + */ +/* reload value when timer count to zero */ +#define TIMER_LOAD_VAL 0xFFFFFFFF + - /* SPL memory allocation configuration, this is for FAT implementation */ - #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 - +/* The rest of the configuration is shared */ +#include + +#endif /* __SOCFGPA_CHAMELEONV3_H__ */ diff --cc scripts/config_whitelist.txt index c61df4fb1c,f4ae48d265..efc2f3bcf7 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@@ -493,7 -389,8 +389,6 @@@ CONFIG_RAMBOOT_TEXT_BAS CONFIG_RAMDISK_ADDR CONFIG_RD_LVL CONFIG_RESET_VECTOR_ADDRESS - CONFIG_RESTORE_FLASH -CONFIG_ROCKCHIP_CHIP_TAG -CONFIG_ROCKCHIP_MAX_INIT_SIZE CONFIG_ROCKCHIP_SDHCI_MAX_FREQ CONFIG_ROOTPATH CONFIG_RTC_DS1337