From: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Date: Wed, 14 Jun 2023 12:04:52 +0000 (-0600)
Subject: cadence_qspi: Enable flash reset for Versal NET platform
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=34dec6a443df2adb5df2c65b2c441652c5976b44;p=u-boot.git

cadence_qspi: Enable flash reset for Versal NET platform

Enable flash reset functionality for Versal NET platform.
In cadence_qspi.c there is weak function defined for reset, hence remove
the check for config, so that it will work for Versal and Versal NET
platforms.

Add register defines in Versal NET hardware.h for mini U-Boot flash
reset.

Add read_delay initialization for Versal NET also.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230614120452.21019-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h
index 3f04104961..9bddb8b007 100644
--- a/arch/arm/mach-versal-net/include/mach/hardware.h
+++ b/arch/arm/mach-versal-net/include/mach/hardware.h
@@ -81,3 +81,14 @@ enum versal_net_platform {
 #define VERSAL_SLCR_BASEADDR	0xF1060000
 #define VERSAL_AXI_MUX_SEL	(VERSAL_SLCR_BASEADDR + 0x504)
 #define VERSAL_OSPI_LINEAR_MODE	BIT(1)
+
+#define FLASH_RESET_GPIO	0xc
+#define WPROT_CRP	0xF126001C
+#define RST_GPIO	0xF1260318
+#define WPROT_LPD_MIO	0xFF080728
+#define WPROT_PMC_MIO	0xF1060828
+#define BOOT_MODE_DIR	0xF1020204
+#define BOOT_MODE_OUT	0xF1020208
+#define MIO_PIN_12	0xF1060030
+#define BANK0_OUTPUT	0xF1020040
+#define BANK0_TRI	0xF1060200
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index 434c6038f3..a7685a2f51 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -130,7 +130,6 @@ int cadence_qspi_apb_wait_for_dma_cmplt(struct cadence_spi_priv *priv)
 #if defined(CONFIG_DM_GPIO)
 int cadence_qspi_versal_flash_reset(struct udevice *dev)
 {
-#ifndef CONFIG_ARCH_VERSAL_NET
 	struct gpio_desc gpio;
 	u32 reset_gpio;
 	int ret;
@@ -166,7 +165,7 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev)
 	/* Set value 1 to pin */
 	dm_gpio_set_value(&gpio, 1);
 	udelay(1);
-#endif
+
 	return 0;
 }
 #else
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 2d715e478c..cc3a54f295 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -249,17 +249,14 @@ static int cadence_spi_probe(struct udevice *bus)
 
 	priv->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, priv->ref_clk_hz);
 
-	if (IS_ENABLED(CONFIG_ARCH_VERSAL)) {
-		/* Versal platform uses spi calibration to set read delay */
+	/* Versal and Versal-NET use spi calibration to set read delay */
+	if (CONFIG_IS_ENABLED(ARCH_VERSAL) ||
+	    CONFIG_IS_ENABLED(ARCH_VERSAL_NET))
 		if (priv->read_delay >= 0)
 			priv->read_delay = -1;
-		/* Reset ospi flash device */
-		ret = cadence_qspi_versal_flash_reset(bus);
-		if (ret)
-			return ret;
-	}
 
-	return 0;
+	/* Reset ospi flash device */
+	return cadence_qspi_versal_flash_reset(bus);
 }
 
 static int cadence_spi_remove(struct udevice *dev)