From: Minda Chen <minda.chen@starfivetech.com>
Date: Thu, 20 Jul 2023 11:37:27 +0000 (+0800)
Subject: net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=309484516576d74e0868ac6399b36e56e9d30a3e;p=u-boot.git

net: rtl8169: Fix DMA minimal aligned compile warning in RISC-V

For RISC-V architeture, hardware maintain the dcache coherency.
Software do not flush the cache. So even cache-line size larger
than descriptor size, driver can work.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index dcba51590d..34e4cff1e9 100644
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
  *
  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  * the driver to allocate descriptors from a pool of non-cached memory.
+ *
+ * Hardware maintain D-cache coherency in RISC-V architecture.
  */
 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-	!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+	!CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
 #warning cache-line size is larger than descriptor size
 #endif
 #endif