From: Stefan Roese <sr@denx.de>
Date: Thu, 14 May 2020 09:59:03 +0000 (+0200)
Subject: mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=2eed3dca229e97aa03954ee5178457c4f2f8cfdb;p=u-boot.git

mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM

This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h
index 3878171607..99ddbccd80 100644
--- a/arch/mips/include/asm/cm.h
+++ b/arch/mips/include/asm/cm.h
@@ -41,6 +41,7 @@
 #include <asm/io.h>
 #include <linux/bitops.h>
 
+#if CONFIG_IS_ENABLED(MIPS_CM)
 static inline void *mips_cm_base(void)
 {
 	return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE);
@@ -56,6 +57,17 @@ static inline unsigned long mips_cm_l2_line_size(void)
 	line_sz &= GENMASK(GCR_L2_CONFIG_LINESZ_BITS - 1, 0);
 	return line_sz ? (2 << line_sz) : 0;
 }
+#else
+static inline void *mips_cm_base(void)
+{
+	return NULL;
+}
+
+static inline unsigned long mips_cm_l2_line_size(void)
+{
+	return 0;
+}
+#endif
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 24f115ebc9..b5c42aeed7 100644
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -8,9 +8,7 @@
 #include <cpu_func.h>
 #include <asm/cache.h>
 #include <asm/cacheops.h>
-#ifdef CONFIG_MIPS_L2_CACHE
 #include <asm/cm.h>
-#endif
 #include <asm/io.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>