From: Pali Rohár Date: Sat, 31 Jul 2021 12:22:53 +0000 (+0200) Subject: arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=2ddf554b8648d892efc5733e7486cec5e93dc269;p=u-boot.git arm: mvebu: a37x: Detect CONFIG_SYS_TCLK from SAR register Bit 20 in SAR register specifies if TCLK is running at 200 MHz or 166 MHz. Use this information instead of manual configuration in every board file. Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese --- diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index cb323aa59a..eb6906ad80 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -145,6 +145,9 @@ #define BOOT_FROM_UART 0x30 #define BOOT_FROM_SPI 0x38 + +#define CONFIG_SYS_TCLK ((readl(CONFIG_SAR_REG) & BIT(20)) ? \ + 200000000 : 166000000) #elif defined(CONFIG_ARMADA_38X) /* SAR values for Armada 38x */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18600)) diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h index 410a40af3e..18f4707e6b 100644 --- a/include/configs/db-88f6720.h +++ b/include/configs/db-88f6720.h @@ -15,7 +15,6 @@ * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ /* I2C */ #define CONFIG_SYS_I2C_LEGACY