From: Marek Vasut <marex@denx.de>
Date: Thu, 9 Jul 2015 01:52:12 +0000 (+0200)
Subject: arm: socfpga: reset: Repair bridge reset handling
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=292260ca21723ab78d23fa2cf6b574cf17778991;p=u-boot.git

arm: socfpga: reset: Repair bridge reset handling

The current bridge reset code, which de-asserted the bridge reset,
was activelly polling whether the FPGA is programmed and ready and
in case it was (!), the code called hang(). This makes no sense at
all. Repair it such that the code instead checks whether the FPGA
is programmed, but without any polling involved, and only if it is
programmed, it de-asserts the reset.

Signed-off-by: Marek Vasut <marex@denx.de>
---

diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index 18af25ced1..6a11c19200 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -85,10 +85,10 @@ void socfpga_bridges_reset(int enable)
 		writel(0xffffffff, &reset_manager_base->brg_mod_reset);
 	} else {
 		/* Check signal from FPGA. */
-		if (fpgamgr_poll_fpga_ready()) {
-			/* FPGA not ready. Wait for watchdog timeout. */
-			printf("%s: fpga not ready, hanging.\n", __func__);
-			hang();
+		if (!fpgamgr_test_fpga_ready()) {
+			/* FPGA not ready, do nothing. */
+			printf("%s: FPGA not ready, aborting.\n", __func__);
+			return;
 		}
 
 		/* brdmodrst */