From: Luka Kovacic Date: Tue, 7 May 2019 17:35:55 +0000 (+0200) Subject: arm: mvebu: Add CRS305-1G-4S board X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=22bb913fdf14476b60e1ae86321567116dea5ed7;p=u-boot.git arm: mvebu: Add CRS305-1G-4S board CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some of the other similar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently retrieved from the stock bootloader and compiled into the kwb image. Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip support and writing env to SPI flash. Signed-off-by: Luka Kovacic Reviewed-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 8b971434eb..56bf5aa8de 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -162,7 +162,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \ armada-38x-controlcenterdc.dtb \ armada-385-atl-x530.dtb \ armada-385-atl-x530DP.dtb \ - armada-xp-db-xc3-24g4xg.dtb + armada-xp-db-xc3-24g4xg.dtb \ + armada-xp-crs305-1g-4s.dtb dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ uniphier-ld11-global.dtb \ diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi new file mode 100644 index 0000000000..8576a02730 --- /dev/null +++ b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&spi0 { + u-boot,dm-pre-reloc; + + spi-flash@0 { + u-boot,dm-pre-reloc; + }; +}; diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s.dts b/arch/arm/dts/armada-xp-crs305-1g-4s.dts new file mode 100644 index 0000000000..1116f5c96c --- /dev/null +++ b/arch/arm/dts/armada-xp-crs305-1g-4s.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree file for CRS305-1G-4S board + * + * Copyright (C) 2016 Allied Telesis Labs + * + * Based on armada-xp-db.dts + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. + */ + +/dts-v1/; +#include "armada-xp-98dx3236.dtsi" +#include "armada-xp-crs305-1g-4s-u-boot.dtsi" + +/ { + model = "CRS305-1G-4S"; + compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "console=ttyS0,115200 earlyprintk"; + }; + + aliases { + spi0 = &spi0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x20000000>; /* 512 MB */ + }; +}; + +&L2 { + arm,parity-enable; + marvell,ecc-enable; +}; + +&devbus_bootcs { + status = "okay"; + + /* Device Bus parameters are required */ + + /* Read parameters */ + devbus,bus-width = <16>; + devbus,turn-off-ps = <60000>; + devbus,badr-skew-ps = <0>; + devbus,acc-first-ps = <124000>; + devbus,acc-next-ps = <248000>; + devbus,rd-setup-ps = <0>; + devbus,rd-hold-ps = <0>; + + /* Write parameters */ + devbus,sync-enable = <0>; + devbus,wr-high-ps = <60000>; + devbus,wr-low-ps = <60000>; + devbus,ale-wr-ps = <60000>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + m25p,fast-read; + + partition@u-boot { + reg = <0x00000000 0x00100000>; + label = "u-boot"; + }; + partition@u-boot-env { + reg = <0x00100000 0x00040000>; + label = "u-boot-env"; + }; + partition@unused { + reg = <0x00140000 0x00ec0000>; + label = "unused"; + }; + + }; +}; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index a832e1dc8c..495c48e6c7 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -164,6 +164,10 @@ config TARGET_DB_XC3_24G4XG bool "Support DB-XC3-24G4XG" select 98DX3336 +config TARGET_CRS305_1G_4S + bool "Support CRS305-1G-4S" + select 98DX3236 + endchoice config SYS_BOARD @@ -183,6 +187,7 @@ config SYS_BOARD default "a38x" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG + default "crs305-1g-4s" if TARGET_CRS305_1G_4S config SYS_CONFIG_NAME default "clearfog" if TARGET_CLEARFOG @@ -201,6 +206,7 @@ config SYS_CONFIG_NAME default "controlcenterdc" if TARGET_CONTROLCENTERDC default "x530" if TARGET_X530 default "db-xc3-24g4xg" if TARGET_DB_XC3_24G4XG + default "crs305-1g-4s" if TARGET_CRS305_1G_4S config SYS_VENDOR default "Marvell" if TARGET_DB_MV784MP_GP @@ -218,6 +224,7 @@ config SYS_VENDOR default "CZ.NIC" if TARGET_TURRIS_MOX default "gdsys" if TARGET_CONTROLCENTERDC default "alliedtelesis" if TARGET_X530 + default "mikrotik" if TARGET_CRS305_1G_4S config SYS_SOC default "mvebu" diff --git a/board/mikrotik/crs305-1g-4s/.gitignore b/board/mikrotik/crs305-1g-4s/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/mikrotik/crs305-1g-4s/MAINTAINERS b/board/mikrotik/crs305-1g-4s/MAINTAINERS new file mode 100644 index 0000000000..3823489600 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/MAINTAINERS @@ -0,0 +1,7 @@ +CRS305-1G-4S BOARD +M: Luka Kovacic +S: Maintained +F: board/mikrotik/crs305-1g-4s/ +F: include/configs/crs305-1g-4s.h +F: configs/crs305-1g-4s_defconfig +F: arch/arm/dts/armada-xp-crs305-1g-4s.dts diff --git a/board/mikrotik/crs305-1g-4s/Makefile b/board/mikrotik/crs305-1g-4s/Makefile new file mode 100644 index 0000000000..895331beb8 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/Makefile @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2015 Stefan Roese + +obj-y := crs305-1g-4s.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg =-e "s|^BINARY.*|BINARY $(srctree)/$(@D)/binary.0 0000005b 00000068|" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/mikrotik/crs305-1g-4s/README b/board/mikrotik/crs305-1g-4s/README new file mode 100644 index 0000000000..f420aabfbf --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/README @@ -0,0 +1,23 @@ +MikroTik CRS305-1G-4S+IN +======================== + +CRS305-1G-4S+IN is a 4x SFP+ switch with a Gigabit Ethernet port for management. +Specifications: + - Marvell Prestera 98DX3236 switch with an integrated ARMv7 CPU + - 512 MB DDR3 RAM + - UART @ 115200bps + - 4x SFP+ + - Gigabit Ethernet (AR8033) + - 16 MB SPI flash (Winbond 25Q128JVSM) + +Currently supported hardware: + - UART boot (using kwboot) and console + - SPI boot, environment and load kernel + +Planned: + - Gigabit Ethernet support + +Getting binary.0 +================ +binary.0 (DDR3 init phase) can be retrieved/extracted from the integrated bootloader on the SPI flash. +Then binary.0 can be replaced with the extracted blob. diff --git a/board/mikrotik/crs305-1g-4s/binary.0 b/board/mikrotik/crs305-1g-4s/binary.0 new file mode 100644 index 0000000000..8dd687286a --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/binary.0 @@ -0,0 +1,11 @@ +-------- +WARNING: +-------- +This file should contain the bin_hdr generated by the original Marvell +U-Boot implementation. As this is currently not included in this +U-Boot version, we have added this placeholder, so that the U-Boot +image can be generated without errors. + +If you have a known to be working bin_hdr for your board, then you +just need to replace this text file here with the binary header +and recompile U-Boot. diff --git a/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c new file mode 100644 index 0000000000..d1d1f40092 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/crs305-1g-4s.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Stefan Roese + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * These values and defines are taken from the Marvell U-Boot version + * "u-boot-2013.01-2016_T1.0.eng_drop_v6" + */ +#define DB_DX_AC3_GPP_OUT_ENA_LOW (~(BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30))) +#define DB_DX_AC3_GPP_OUT_ENA_MID (~(0)) +#define DB_DX_AC3_GPP_OUT_VAL_LOW (BIT(0) | BIT(2) | BIT(3) | BIT(4) \ + | BIT(6) | BIT(12) | BIT(13) \ + | BIT(16) | BIT(17) | BIT(20) \ + | BIT(29) | BIT(30)) +#define DB_DX_AC3_GPP_OUT_VAL_MID 0x0 +#define DB_DX_AC3_GPP_POL_LOW 0x0 +#define DB_DX_AC3_GPP_POL_MID 0x0 + +int board_early_init_f(void) +{ + /* Configure MPP */ + writel(0x00142222, MVEBU_MPP_BASE + 0x00); + writel(0x11122000, MVEBU_MPP_BASE + 0x04); + writel(0x44444004, MVEBU_MPP_BASE + 0x08); + writel(0x14444444, MVEBU_MPP_BASE + 0x0c); + writel(0x00000001, MVEBU_MPP_BASE + 0x10); + + /* + * MVEBU_GPIO0_BASE is the User LED + * MVEBU_GPIO1_BASE is the Reset Button (currently not used) + */ + + /* Set GPP Out value */ + writel(DB_DX_AC3_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); + /* writel(DB_DX_AC3_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); */ + + /* Set GPP Polarity */ + writel(DB_DX_AC3_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); + /* writel(DB_DX_AC3_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); */ + + /* Set GPP Out Enable */ + writel(DB_DX_AC3_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); + /* writel(DB_DX_AC3_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); */ + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_SYS_BOARD "\n"); + + return 0; +} diff --git a/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in new file mode 100644 index 0000000000..2dbbbd0246 --- /dev/null +++ b/board/mikrotik/crs305-1g-4s/kwbimage.cfg.in @@ -0,0 +1,12 @@ +# +# Copyright (C) 2014 Stefan Roese +# + +# Armada XP uses version 1 image format +VERSION 1 + +# Boot Media configurations +BOOT_FROM spi + +# Binary Header (bin_hdr) with DDR3 training code +BINARY board/mikrotik/crs305-1g-4s/binary.0 0000005b 00000068 diff --git a/configs/crs305-1g-4s_defconfig b/configs/crs305-1g-4s_defconfig new file mode 100644 index 0000000000..66ba04ede8 --- /dev/null +++ b/configs/crs305-1g-4s_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_MVEBU=y +CONFIG_SYS_TEXT_BASE=0x00800000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_TARGET_CRS305_1G_4S=y +CONFIG_BUILD_TARGET="u-boot.kwb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +# CONFIG_CMD_USB is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_UBI=y +CONFIG_DEFAULT_DEVICE_TREE="armada-xp-crs305-1g-4s" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BLK=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MVTWSI=y +# CONFIG_MMC is not set +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +# CONFIG_NAND is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PCI=y +CONFIG_PCI_MVEBU=y +CONFIG_SYS_NS16550=y +CONFIG_KIRKWOOD_SPI=y +# CONFIG_USB is not set +# CONFIG_DM_USB is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_HOST_ETHER is not set diff --git a/include/configs/crs305-1g-4s.h b/include/configs/crs305-1g-4s.h new file mode 100644 index 0000000000..c73cb99b1b --- /dev/null +++ b/include/configs/crs305-1g-4s.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Stefan Roese + */ + +#ifndef _CONFIG_CRS305_1G_4S_H +#define _CONFIG_CRS305_1G_4S_H + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +/* USB/EHCI configuration */ +#define CONFIG_EHCI_IS_TDI + +/* Environment in SPI NOR flash */ +#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ +#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ +#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ + +/* Keep device tree and initrd in lower memory so the kernel can access them */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x10000000\0" \ + "initrd_high=0x10000000\0" + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" +#undef CONFIG_SYS_MAXARGS +#define CONFIG_SYS_MAXARGS 96 + +#endif /* _CONFIG_CRS305_1G_4S_H */