From: Nava kishore Manne <nava.manne@xilinx.com>
Date: Fri, 18 Oct 2019 16:07:32 +0000 (+0200)
Subject: arm64: zynqmp: Sync zynqmp fpga manager with mainline
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=21620990cf7ed6a5e0354db2942a31e69cdf6b6f;p=u-boot.git

arm64: zynqmp: Sync zynqmp fpga manager with mainline

Sync zynqmp fpga manager with mainline.

Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi
index 1098e89019..0b0fb6e987 100644
--- a/arch/arm/dts/zynqmp-clk-ccf.dtsi
+++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi
@@ -291,3 +291,7 @@
 &xlnx_dp_snd_codec0 {
 	clocks = <&zynqmp_clk DP_AUDIO_REF>;
 };
+
+&zynqmp_pcap {
+	clocks = <&zynqmp_clk PCAP>;
+};
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index ec0dd73e15..58ac62c4f8 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -149,6 +149,11 @@
 			#power-domain-cells = <0x1>;
 			u-boot,dm-pre-reloc;
 
+			zynqmp_pcap: pcap {
+				compatible = "xlnx,zynqmp-pcap-fpga";
+				clock-names = "ref_clk";
+			};
+
 			zynqmp_power: zynqmp-power {
 				u-boot,dm-pre-reloc;
 				compatible = "xlnx,zynqmp-power";
@@ -180,9 +185,10 @@
 
 	fpga_full: fpga-full {
 		compatible = "fpga-region";
-		fpga-mgr = <&pcap>;
+		fpga-mgr = <&zynqmp_pcap>;
 		#address-cells = <2>;
 		#size-cells = <2>;
+		ranges;
 	};
 
 	nvmem_firmware {
@@ -195,10 +201,6 @@
 		};
 	};
 
-	pcap: pcap {
-		compatible = "xlnx,zynqmp-pcap-fpga";
-	};
-
 	rst: reset-controller {
 		compatible = "xlnx,zynqmp-reset";
 		#reset-cells = <1>;