From: Tom Rini Date: Fri, 18 Mar 2022 12:38:26 +0000 (-0400) Subject: Convert CONFIG_PHY_RESET_DELAY to Kconfig X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=16199a8b961fab60587011e9da5a592b94d3eaf4;p=u-boot.git Convert CONFIG_PHY_RESET_DELAY to Kconfig This converts the following to Kconfig: CONFIG_PHY_RESET_DELAY Cc: Ramon Fried Signed-off-by: Tom Rini --- diff --git a/README b/README index effaef5574..0072e03b63 100644 --- a/README +++ b/README @@ -1075,13 +1075,6 @@ The following options need to be configured: The clock frequency of the MII bus - CONFIG_PHY_RESET_DELAY - - Some PHY like Intel LXT971A need extra delay after - reset before any MII register access is possible. - For such PHY, set this option to the usec delay - required. (minimum 300usec for LXT971A) - CONFIG_PHY_CMD_DELAY (ppc4xx) Some PHY like Intel LXT971A need extra delay after diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index 27f30d1d2e..327c0e0697 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -19,7 +19,4 @@ #define CONFIG_SYS_NS16550_CLK_DIV 54 #define CONFIG_SYS_NS16550_COM3 0x18023000 -/* Ethernet */ -#define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ - #endif /* __ARCH_CONFIGS_H */ diff --git a/common/miiphyutil.c b/common/miiphyutil.c index 7d4d15ed91..194c84e7e8 100644 --- a/common/miiphyutil.c +++ b/common/miiphyutil.c @@ -366,7 +366,7 @@ int miiphy_reset(const char *devname, unsigned char addr) debug("PHY reset failed\n"); return -1; } -#ifdef CONFIG_PHY_RESET_DELAY +#if CONFIG_PHY_RESET_DELAY > 0 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ #endif /* diff --git a/configs/bcm968380gerg_ram_defconfig b/configs/bcm968380gerg_ram_defconfig index 7eb23bdc62..95cce92e92 100644 --- a/configs/bcm968380gerg_ram_defconfig +++ b/configs/bcm968380gerg_ram_defconfig @@ -49,6 +49,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6838=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_PHY=y CONFIG_BCM6368_USBH_PHY=y CONFIG_PINCTRL=y diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index 45e8b76583..9268aea02a 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 5a944483d0..9d2fc0cbf1 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 6290b2a720..ddb12508bf 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 35bc13964e..b2973fa0f3 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -52,6 +52,7 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_BRCMNAND=y CONFIG_NAND_BRCMNAND_6368=y CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6368_ETH=y CONFIG_PHY=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index a2e5f9648c..5ad85b10f5 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -50,6 +50,7 @@ CONFIG_CFI_FLASH=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_BCM6368_ETH=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index 977450e351..261e1bf693 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index b961b58ac3..869d4c8e4e 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -45,6 +45,7 @@ CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y CONFIG_DM_SERIAL=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig index c3e626c9c3..8649f0ecd9 100644 --- a/configs/netgear_dgnd3700v2_ram_defconfig +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -47,6 +47,7 @@ CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y CONFIG_LED_GPIO=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_BCM6368_ETH=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index ac906a9dcf..9ac5dbaae1 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_DM_RESET=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 5caad90fe9..e97c1f06bd 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y CONFIG_PHY_FIXED=y +CONFIG_PHY_RESET_DELAY=20 CONFIG_DM_ETH=y CONFIG_BCM6348_ETH=y CONFIG_PHY=y diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index fa1ae10838..7b40329405 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -35,6 +35,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_PHY_RESET_DELAY=10000 CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y CONFIG_CADENCE_QSPI=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 74339a25ca..eed6eb1866 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -330,3 +330,11 @@ config PHY_NCSI depends on DM_ETH endif #PHYLIB + +config PHY_RESET_DELAY + int "Extra delay after reset before MII register access" + default 0 + help + Some PHYs need extra delay after reset before any MII register access + is possible. For such PHY, set this option to the usec delay + required. diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index fffa10f68b..92fff5b72c 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -872,7 +872,7 @@ int phy_reset(struct phy_device *phydev) return -1; } -#ifdef CONFIG_PHY_RESET_DELAY +#if CONFIG_PHY_RESET_DELAY > 0 udelay(CONFIG_PHY_RESET_DELAY); /* Intel LXT971A needs this */ #endif /* diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h index 57de996095..0c357dea9d 100644 --- a/include/configs/bmips_common.h +++ b/include/configs/bmips_common.h @@ -8,9 +8,6 @@ #include -/* ETH */ -#define CONFIG_PHY_RESET_DELAY 20 - /* UART */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ 230400, 500000, 1500000 } diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index dd94216876..feec8695f2 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -29,9 +29,6 @@ #define CONFIG_DW_ALTDESCRIPTOR -/* Command support defines */ -#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ - /* Misc configuration */ /*