From: Dinesh Maniyam <dinesh.maniyam@intel.com>
Date: Thu, 7 Dec 2023 07:46:02 +0000 (+0800)
Subject: arm: socfpga: stratix10: SPI clock support
X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=158d648d9f02c9ee0f432bbafeea38aaa55dd943;p=u-boot.git

arm: socfpga: stratix10: SPI clock support

This patch is to add SPI clock support for stratix10. Get clock rate
function always returning 0 because the DW-SPI driver get the rate
from clock node in dts but Stratix10 does not support device tree
clock node.To overcome this spi will get the clock_rate directly
from spi clock controller override the weaker function.

Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
---

diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c
index 4b4f0749db..45300336d5 100644
--- a/arch/arm/mach-socfpga/clock_manager_s10.c
+++ b/arch/arm/mach-socfpga/clock_manager_s10.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2023 Intel Corporation <www.intel.com>
  *
  */
 
@@ -399,6 +399,21 @@ unsigned int cm_get_l4_sys_free_clk_hz(void)
 	return cm_get_l3_main_clk_hz() / 4;
 }
 
+/*
+ * Override weak dw_spi_get_clk implementation in designware_spi.c driver
+ */
+
+int dw_spi_get_clk(struct udevice *bus, ulong *rate)
+{
+	*rate = cm_get_spi_controller_clk_hz();
+	if (!*rate) {
+		printf("SPI: clock rate is zero");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 void cm_print_clock_quick_summary(void)
 {
 	printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));