From: Chin Liang See Date: Wed, 21 Sep 2016 02:26:03 +0000 (+0800) Subject: arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1 X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=13022d852d5c233894fabb62279a2ae9e0355638;p=u-boot.git arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1 Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See Cc: Marek Vasut Cc: Dinh Nguyen --- diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h index 7084797750..d96b28af82 100644 --- a/board/terasic/de0-nano-soc/qts/sdram_config.h +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -42,6 +42,9 @@ #define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 #define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 #define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 #define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 #define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0