From: wdenk Date: Sun, 6 Jun 2004 21:35:06 +0000 (+0000) Subject: Patch by Yuli Barcohen, 19 Apr 2004: X-Git-Url: http://git.dujemihanovic.xyz/?a=commitdiff_plain;h=1114257c9df3fa3db39ff55dd03d1f7cbc5c0603;p=u-boot.git Patch by Yuli Barcohen, 19 Apr 2004: - Rename DUET_ADS to MPC885ADS - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY - Clean up FADS family port to use the new defines --- diff --git a/CHANGELOG b/CHANGELOG index 3610e92d1f..519e97741b 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,12 @@ Changes since U-Boot 1.1.1: ====================================================================== +* Patch by Yuli Barcohen, 19 Apr 2004: + - Rename DUET_ADS to MPC885ADS + - Rename CONFIG_DUET to CONFIG_MPC885_FAMILY + - Rename CONFIG_866_et_al to CONFIG_MPC866_FAMILY + - Clean up FADS family port to use the new defines + * Fix PCI support on CPC45 board * Patch by Scott McNutt, 25 Apr 2004: diff --git a/MAKEALL b/MAKEALL index d0dd2235c3..7c1576b0b6 100644 --- a/MAKEALL +++ b/MAKEALL @@ -34,7 +34,7 @@ LIST_5xxx=" \ LIST_8xx=" \ AdderII ADS860 AMX860 c2mon \ - CCM cogent_mpc8xx DUET_ADS ESTEEM192E \ + CCM cogent_mpc8xx MPC885ADS ESTEEM192E \ ETX094 ELPT860 FADS823 FADS850SAR \ FADS860T FLAGADM FPS850L GEN860T \ GEN860T_SC GENIETV GTH hermes \ diff --git a/Makefile b/Makefile index a55d88a169..7b84baf629 100644 --- a/Makefile +++ b/Makefile @@ -266,10 +266,10 @@ AdderII_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx adderII ADS860_config \ -DUET_ADS_config \ FADS823_config \ FADS850SAR_config \ MPC86xADS_config \ +MPC885ADS_config \ FADS860T_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx fads diff --git a/board/fads/config.mk b/board/fads/config.mk index dcf83fbea7..621b9a2493 100644 --- a/board/fads/config.mk +++ b/board/fads/config.mk @@ -24,8 +24,8 @@ # # -# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and DUET -# (MPC87x/88x) ADS boards +# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and +# MPC885ADS boards # TEXT_BASE = 0xFE000000 diff --git a/board/fads/fads.c b/board/fads/fads.c index 1507146366..013b3cb155 100644 --- a/board/fads/fads.c +++ b/board/fads/fads.c @@ -26,12 +26,13 @@ #include #include #include +#include #define _NOT_USED_ 0xFFFFFFFF /* ========================================================================= */ -#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */ +#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ #if defined(CONFIG_DRAM_50MHZ) /* 50MHz tables */ @@ -290,7 +291,7 @@ static void _dramdisable(void) /* maybe we should turn off upma here or something */ } -#endif /* !CONFIG_DUET_ADS */ +#endif /* !CONFIG_MPC885ADS */ /* ========================================================================= */ @@ -604,7 +605,7 @@ long int initdram (int board_type) uint sdramsz = 0; /* size of sdram in Mbytes */ uint base = 0; /* base of dram in bytes */ uint m = 0; /* size of dram in Mbytes */ -#ifndef CONFIG_DUET_ADS +#ifndef CONFIG_MPC885ADS uint k, s; #endif @@ -614,7 +615,7 @@ long int initdram (int board_type) printf ("(%u MB SDRAM) ", sdramsz); } #endif -#ifndef CONFIG_DUET_ADS /* No old DRAM on Duet */ +#ifndef CONFIG_MPC885ADS /* No old DRAM on MPC885ADS */ k = (*((uint *) BCSR2) >> 23) & 0x0f; switch (k & 0x3) { @@ -665,7 +666,7 @@ long int initdram (int board_type) _dramdisable (); m = 0; } -#endif /* !CONFIG_DUET_ADS */ +#endif /* !CONFIG_MPC885ADS */ m += sdramsz; /* add sdram size to total */ return (m << 20); @@ -734,8 +735,8 @@ int checkboard (void) #if defined(CONFIG_MPC86xADS) puts ("MPC86xADS"); -#elif defined(CONFIG_DUET_ADS) - puts ("DUET ADS"); +#elif defined(CONFIG_MPC885ADS) + puts ("MPC885ADS"); r = 0; /* I've got NR (No Revision) board */ #elif defined(CONFIG_FADS) puts ("FADS"); @@ -759,7 +760,7 @@ int checkboard (void) case 0x03: puts ("B \n"); break; -#elif defined(CONFIG_DUET_ADS) +#elif defined(CONFIG_MPC885ADS) case 0x00: puts ("NR\n"); break; @@ -790,7 +791,7 @@ volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR; int pcmcia_init(void) { volatile pcmconf8xx_t *pcmp; - uint v, slota, slotb; + uint v, slota = 0, slotb = 0; /* ** Enable the PCMCIA for a Flash card. @@ -805,10 +806,10 @@ int pcmcia_init(void) /* Set all slots to zero by default. */ pcmp->pcmc_pgcra = 0; pcmp->pcmc_pgcrb = 0; -#ifdef PCMCIA_SLOT_A +#ifdef CONFIG_PCMCIA_SLOT_A pcmp->pcmc_pgcra = 0x40; #endif -#ifdef PCMCIA_SLOT_B +#ifdef CONFIG_PCMCIA_SLOT_B pcmp->pcmc_pgcrb = 0x40; #endif @@ -817,17 +818,17 @@ int pcmcia_init(void) /* Check if any PCMCIA card is plugged in. */ +#ifdef CONFIG_PCMCIA_SLOT_A slota = (pcmp->pcmc_pipr & 0x18000000) == 0 ; +#endif +#ifdef CONFIG_PCMCIA_SLOT_B slotb = (pcmp->pcmc_pipr & 0x00001800) == 0 ; +#endif if (!(slota || slotb)) { printf("No card present\n"); -#ifdef PCMCIA_SLOT_A pcmp->pcmc_pgcra = 0; -#endif -#ifdef PCMCIA_SLOT_B pcmp->pcmc_pgcrb = 0; -#endif return -1; } else @@ -908,9 +909,10 @@ int pcmcia_init(void) udelay(20); -#ifdef PCMCIA_SLOT_A +#ifdef CONFIG_PCMCIA_SLOT_A pcmp->pcmc_pgcra = 0; -#elif PCMCIA_SLOT_B +#endif +#ifdef CONFIG_PCMCIA_SLOT_B pcmp->pcmc_pgcrb = 0; #endif diff --git a/board/fads/fads.h b/board/fads/fads.h index 668b906d56..d4e9f02c3a 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -48,9 +48,6 @@ * | ... | v * *****************************************************************************/ -/* should ALWAYS define this, measure_gclk in speed.c is unreliable */ -/* in general, we always know this for FADS+new ADS anyway */ -#define CONFIG_8xx_GCLK_FREQ ((CFG_8XX_XIN) * (CFG_8XX_FACT)) #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -66,6 +63,7 @@ "bootm" #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ /* * New MPC86xADS and Duet provide two Ethernet connectivity options: @@ -90,11 +88,12 @@ #endif #ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PCMCIA \ + | CFG_CMD_PING \ ) #endif /* !CONFIG_COMMANDS */ @@ -146,7 +145,7 @@ * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#if defined(CONFIG_MPC86xADS) || defined(CONFIG_DUET_ADS) /* New ADS or Duet */ +#if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */ #define CFG_SDRAM_SIZE 0x00800000 /* 8 Mbyte */ #elif defined(CONFIG_FADS) /* Old/new FADS */ #define CFG_SDRAM_SIZE 0x00400000 /* 4 Mbyte */ @@ -186,7 +185,12 @@ #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ + +#ifdef CONFIG_BZIP2 +#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ +#else #define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ +#endif /* CONFIG_BZIP2 */ /*----------------------------------------------------------------------- * Cache Configuration @@ -248,7 +252,16 @@ #define SCCR_MASK SCCR_EBDF11 #define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00) - /*----------------------------------------------------------------------- +/*----------------------------------------------------------------------- + * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 + *----------------------------------------------------------------------- + * set the PLL, the low-power modes and the reset control + */ +#ifndef CFG_PLPRCR +#define CFG_PLPRCR PLPRCR_TEXPS +#endif + +/*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * @@ -407,6 +420,20 @@ #define BCSR4_DATA_VOICE ((uint)0x00080000) #endif /* CONFIG_MPC850 */ +/* BSCR5 exists on MPC86xADS and Duet ADS only */ + +#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) + +#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) + +#define BCSR5_MII2_EN 0x40 +#define BCSR5_MII2_RST 0x20 +#define BCSR5_T1_RST 0x10 +#define BCSR5_ATM155_RST 0x08 +#define BCSR5_ATM25_RST 0x04 +#define BCSR5_MII1_EN 0x02 +#define BCSR5_MII1_RST 0x01 + /* We don't use the 8259. */ #define NR_8259_INTS 0 @@ -419,10 +446,6 @@ * PCMCIA stuff *----------------------------------------------------------------------- */ -#if !defined(CONFIG_MPC823) && !defined(CONFIG_MPC850) -#define PCMCIA_SLOT_A 1 -#endif - #define CFG_PCMCIA_MEM_ADDR (0xE0000000) #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) #define CFG_PCMCIA_DMA_ADDR (0xE4000000) diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 39fe690316..c6b84fae16 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -388,7 +388,7 @@ static void fec_pin_init(int fecidx) fecp->fec_mii_speed <<= 1; #endif -#if defined(CONFIG_DUET) && defined(WANT_MII) +#if defined(CONFIG_MPC885_FAMILY) && defined(WANT_MII) /* use MDC for MII */ immr->im_ioport.iop_pdpar |= 0x0080; immr->im_ioport.iop_pddir &= ~0x0080; @@ -397,7 +397,7 @@ static void fec_pin_init(int fecidx) if (fecidx == 0) { #if defined(CONFIG_ETHER_ON_FEC1) -#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) @@ -489,7 +489,7 @@ static void fec_pin_init(int fecidx) #if defined(CONFIG_ETHER_ON_FEC2) -#if defined(CONFIG_DUET) /* MPC87x/88x have got 2 FECs and different pinout */ +#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */ #if !defined(CONFIG_RMII) @@ -516,7 +516,7 @@ static void fec_pin_init(int fecidx) immr->im_cpm.cp_cptr &= ~0x00000028; #endif /* CONFIG_RMII */ -#endif /* CONFIG_DUET */ +#endif /* CONFIG_MPC885_FAMILY */ #endif /* CONFIG_ETHER_ON_FEC2 */ @@ -533,7 +533,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) if (efis->ether_index == 0) { #if defined(CONFIG_FADS) /* FADS family uses FPGA (BCSR) to control PHYs */ -#if defined(CONFIG_DUET_ADS) +#if defined(CONFIG_MPC885ADS) *(vu_char *) BCSR5 &= ~(BCSR5_MII1_EN | BCSR5_MII1_RST); #else /* configure FADS for fast (FEC) ethernet, half-duplex */ @@ -553,7 +553,7 @@ static int fec_init (struct eth_device *dev, bd_t * bd) *bcsr4 |= BCSR4_FETHRST; udelay (10); } -#endif /* CONFIG_DUET_ADS */ +#endif /* CONFIG_MPC885ADS */ #endif /* CONFIG_FADS */ } @@ -948,7 +948,7 @@ void mii_init (void) */ fecp->fec_ievent = 0xffc0; - /* Setup the pin configuration of the FEC(s) + /* Setup the pin configuration of the FEC(s) */ fec_pin_init(ether_fcc_info[i].ether_index); diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c index 165705cea9..cc011efa4d 100644 --- a/cpu/mpc8xx/speed.c +++ b/cpu/mpc8xx/speed.c @@ -90,7 +90,7 @@ unsigned long measure_gclk(void) ulong timer2_val; ulong msr_val; -#ifdef CONFIG_MPC866_et_al +#ifdef CFG_8XX_XIN /* dont use OSCM, only use EXTCLK/512 */ immr->im_clkrst.car_sccr |= SCCR_RTSEL | SCCR_RTDIV; #else @@ -162,7 +162,7 @@ unsigned long measure_gclk(void) timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2); immr->im_sit.sit_piscr &= ~PISCR_PTE; -#if defined(CONFIG_MPC866_et_al) +#if defined(CFG_8XX_XIN) /* not using OSCM, using XIN, so scale appropriately */ return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L; #else @@ -183,22 +183,39 @@ int get_clocks (void) { DECLARE_GLOBAL_DATA_PTR; - volatile immap_t *immr = (immap_t *) CFG_IMMR; -#ifndef CONFIG_8xx_GCLK_FREQ - gd->cpu_clk = measure_gclk(); -#else /* CONFIG_8xx_GCLK_FREQ */ + uint immr = get_immr (0); /* Return full IMMR contents */ + volatile immap_t *immap = (immap_t *) (immr & 0xFFFF0000); + uint sccr = immap->im_clkrst.car_sccr; /* * If for some reason measuring the gclk frequency won't * work, we return the hardwired value. * (For example, the cogent CMA286-60 CPU module has no * separate oscillator for PITRTCLK) */ - +#if defined(CONFIG_8xx_GCLK_FREQ) gd->cpu_clk = CONFIG_8xx_GCLK_FREQ; - +#elif defined(CONFIG_8xx_OSCLK) +#define PLPRCR_val(a) ((pll & PLPRCR_ ## a ## _MSK) >> PLPRCR_ ## a ## _SHIFT) + uint pll = immap->im_clkrst.car_plprcr; + uint clk; + + if ((immr & 0x0FFF) >= MPC8xx_NEW_CLK) { /* MPC866/87x/88x series */ + clk = ((CONFIG_8xx_OSCLK / (PLPRCR_val(PDF)+1)) * + (PLPRCR_val(MFI) + PLPRCR_val(MFN) / (PLPRCR_val(MFD)+1))) / + (1<cpu_clk = clk / (2 << ((sccr >> 8) & 7)); + } else { /* High frequency division factor is used */ + gd->cpu_clk = clk / (1 << ((sccr >> 5) & 7)); + } +#else + gd->cpu_clk = measure_gclk(); #endif /* CONFIG_8xx_GCLK_FREQ */ - if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) { + if ((sccr & SCCR_EBDF11) == 0) { /* No Bus Divider active */ gd->bus_clk = gd->cpu_clk; } else { @@ -209,7 +226,7 @@ int get_clocks (void) return (0); } -#else /* CONFIG_MPC866_et_al */ +#else /* CONFIG_MPC866_FAMILY */ static long init_pll_866 (long clk); @@ -345,7 +362,7 @@ static long init_pll_866 (long clk) return (n); } -#endif /* CONFIG_MPC866_et_al */ +#endif /* CONFIG_MPC866_FAMILY */ #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) /* diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index 2288115a67..40679cb2b0 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -475,7 +475,7 @@ typedef struct comm_proc { #define lcd_cmap fl_un.fl_un_cmap char res18[0xE00]; - /* The DUET family has a second FEC here */ + /* The MPC885 family has a second FEC here */ fec_t cp_fec2; #define cp_fec1 cp_fec /* consistency macro */ diff --git a/include/common.h b/include/common.h index a7a3a3a7b3..be86426567 100644 --- a/include/common.h +++ b/include/common.h @@ -48,17 +48,17 @@ typedef volatile unsigned char vu_char; defined(CONFIG_MPC859DSL) || \ defined(CONFIG_MPC866) || defined(CONFIG_MPC866T) || \ defined(CONFIG_MPC866P) -# define CONFIG_MPC866_et_al 1 +# define CONFIG_MPC866_FAMILY 1 #elif defined(CONFIG_MPC870) \ || defined(CONFIG_MPC875) \ || defined(CONFIG_MPC880) \ || defined(CONFIG_MPC885) -# define CONFIG_DUET 1 +# define CONFIG_MPC885_FAMILY 1 #endif #if defined(CONFIG_MPC860) \ || defined(CONFIG_MPC860T) \ - || defined(CONFIG_MPC866_et_al) \ - || defined(CONFIG_DUET) + || defined(CONFIG_MPC866_FAMILY) \ + || defined(CONFIG_MPC885_FAMILY) # define CONFIG_MPC86x 1 #endif #elif defined(CONFIG_5xx) diff --git a/include/commproc.h b/include/commproc.h index 9facd771c5..f87620ebf1 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -743,7 +743,8 @@ typedef struct scc_enet { #endif /* CONFIG_SCC1_ETHERNET */ /* - * This ENET stuff is for the MPC860TFADS/MPC86xADS/DUET with ethernet on FEC. + * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS + * with ethernet on FEC. */ #ifdef CONFIG_FEC_ENET diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index 916272dce1..df20965640 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -26,15 +26,17 @@ #define CONFIG_BAUDRATE 38400 /* Console baudrate */ -/* CFG_8XX_FACT * CFG_8XX_XIN = 50 MHz */ #if 0 -#define CFG_8XX_XIN 32768 /* 32.768 kHz input frequency */ -#define CFG_8XX_FACT 0x5F6 /* Multiply by 1526 */ +#define CFG_8XX_FACT 1526 /* 32.768 kHz crystal on XTAL/EXTAL */ #else -#define CFG_8XX_XIN 4000000 /* 4 MHz input frequency */ -#define CFG_8XX_FACT 12 /* Multiply by 12 */ +#define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ #endif +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + +#define CONFIG_DRAM_50MHZ 1 + #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_DHCP \ | CFG_CMD_IMMAP \ @@ -42,13 +44,9 @@ | CFG_CMD_PING \ ) -#define CONFIG_DRAM_50MHZ 1 #include "fads.h" -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - #define CFG_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */ #endif /* __CONFIG_H */ diff --git a/include/configs/FADS860T.h b/include/configs/FADS860T.h index e57571bf3a..18de6b00e7 100644 --- a/include/configs/FADS860T.h +++ b/include/configs/FADS860T.h @@ -27,21 +27,19 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #if 0 /* old FADS */ -# define CFG_8XX_FACT 12 /* Multiply by 12 */ -# define CFG_8XX_XIN 4000000 /* 4 MHz in */ +# define CFG_8XX_FACT 12 /* 4 MHz oscillator on EXTCLK */ #else /* new FADS */ -# define CFG_8XX_FACT 10 /* Multiply by 10 */ -# define CFG_8XX_XIN 5000000 /* 5 MHz in */ +# define CFG_8XX_FACT 10 /* 5 MHz oscillator on EXTCLK */ #endif +#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ + PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) + #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 #include "fads.h" -#define CFG_PLPRCR (((CFG_8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ - PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - #ifdef USE_REAL_FLASH_VALUES /* * These values fit our FADS860T ... @@ -53,6 +51,6 @@ #define CFG_BR0_PRELIM 0x02800001 /* Real values for the board */ #endif -#define CFG_DAUGHTERBOARD /* FADS has processor-specfic daughterboard */ +#define CFG_DAUGHTERBOARD /* FADS has processor-specific daughterboard */ #endif /* __CONFIG_H */ diff --git a/include/configs/MPC86xADS.h b/include/configs/MPC86xADS.h index a6e2606714..565f9bb5c0 100644 --- a/include/configs/MPC86xADS.h +++ b/include/configs/MPC86xADS.h @@ -33,19 +33,14 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -# define CFG_8XX_FACT 5 /* Multiply by 5 */ -# define CFG_8XX_XIN 10000000 /* 10 MHz in */ +#define CONFIG_8xx_OSCLK 10000000 /* 10MHz oscillator on EXTCLK */ #define CONFIG_DRAM_50MHZ 1 #define CONFIG_SDRAM_50MHZ 1 -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) - #include "fads.h" +#define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ +#define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) + #endif /* __CONFIG_H */ diff --git a/include/configs/DUET_ADS.h b/include/configs/MPC885ADS.h similarity index 50% rename from include/configs/DUET_ADS.h rename to include/configs/MPC885ADS.h index 8a4025797d..7f0b06a9fd 100644 --- a/include/configs/DUET_ADS.h +++ b/include/configs/MPC885ADS.h @@ -11,7 +11,7 @@ #define __CONFIG_H /* Board type */ -#define CONFIG_DUET_ADS 1 /* Duet (MPC87x/88x) ADS */ +#define CONFIG_MPC885ADS 1 /* Duet (MPC87x/88x) ADS */ #define CONFIG_FADS 1 /* We are FADS compatible (more or less) */ #define CONFIG_MPC885 1 /* MPC885 CPU (Duet family) */ @@ -21,33 +21,25 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 38400 -#define CFG_8XX_FACT 5 /* Multiply by 5 */ -#define CFG_8XX_XIN 10000000 /* 10 MHz in */ +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ + +#define CFG_PLPRCR ((1 << PLPRCR_MFD_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) #define CONFIG_SDRAM_50MHZ 1 -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 14-22 - *----------------------------------------------------------------------- - * set the PLL, the low-power modes and the reset control - */ -#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | PLPRCR_TEXPS) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_DHCP \ + | CFG_CMD_IMMAP \ + | CFG_CMD_MII \ + | CFG_CMD_PING \ + ) #include "fads.h" -#define CFG_PHYDEV_ADDR (BCSR_ADDR + 0x20000) +#undef CFG_SCCR +#define CFG_SCCR (SCCR_TBS|SCCR_EBDF11) #define CFG_OR5_PRELIM 0xFFFF8110 /* 64Kbyte address space */ #define CFG_BR5_PRELIM (CFG_PHYDEV_ADDR | BR_PS_8 | BR_V) -#define BCSR5 (CFG_PHYDEV_ADDR + 0x300) - -#define BCSR5_MII2_EN 0x40 -#define BCSR5_MII2_RST 0x20 -#define BCSR5_T1_RST 0x10 -#define BCSR5_ATM155_RST 0x08 -#define BCSR5_ATM25_RST 0x04 -#define BCSR5_MII1_EN 0x02 -#define BCSR5_MII1_RST 0x01 - #endif /* __CONFIG_H */